參數(shù)資料
型號(hào)： UPD168113K9-9B4-A
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁(yè)數(shù)： 21/50頁(yè)
文件大?。?/td> 771K
代理商： UPD168113K9-9B4-A
Data Sheet S16423EJ2V0DS
21
μ
PD168113
11.2.2 Pulse output function selection when EXT output
If D6 is set, the function which acts as the monitor of the output state of the driving pulse by the EXT pin can be
selected.
When D6 = 0,
EXT
1
: Output pulse synchronization mode of the micro step output 1
EXT
2
: Output pulse synchronization mode of the micro step output 2
When D6 = 1,
EXT
1
:
Mode with output time of micro step output 1 fixed to H
EXT
2
:
Mode with output time of micro step output 2 fixed to H
The output synchronization mode is duty 50% TYP. in accordance with the pulse frequency setting.
To count the number of pulses, count the rising edges.
11.2.3 Restrictions in pulse output synchronization mode
(1) Output is not guaranteed if the pulse period is
2
μ
s (Db to D0: 000000000001).
(2) Output is equivalent to the H time during steady-state driving (equivalent to pulse period setting) while an
acceleration/deceleration operation is performed.
(3) If the multiplication factor of the number of pulses is set to other than 1, the set number of pulses (address 5 x m)
is output.
11.2.4
Restrictions in mode in which output time is fixed to H
The output falls in synchronization with the falling of the pulse that is to be output at the same timing in the pulse
output synchronization mode.
When the last pulse is output , therefore, it rises earlier than the period of the pulse cycle (50% of pulse cycle or less)
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