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參數(shù)資料
| 型號： | UPD16682W |
| 廠商： | NEC Corp. |
| 英文描述： | 1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 1 / 65稅LCD控制器/驅(qū)動器，片內(nèi)RAM |
| 文件頁數(shù)： | 28/56頁 |
| 文件大小： | 435K |
| 代理商： | UPD16682W |
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Data Sheet S13368EJ3V0DS00
28
μ
PD16682
12.3 Page Address Set
This command specifies the page address corresponding to the row address when accessing the display data RAM
from the MPU side, as was shown in Figure 6
2. The specified bit in display data RAM can be accessed by selecting
the corresponding page address and column address. If the page address is changed, the display mode does not
change.
For details, see
6.2 Page Address Circuit
.
A0
E, /RD
R,/W, /WR
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Page Address
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
↓
↓
0
1
1
1
7
1
0
0
0
8
12.4 Column Address Set
This command specifies the column address in display data RAM, as was shown in Figure 6
2. The column
address is set in a (basically continuous) series of two specifications, one for the high-order four bits and another for
the low-order four bits. The column address is automatically incremented (+1) each time the display data RAM is
accessed, so the MPU is able to continuously read or write display data. Incrementation of the column address stops
at 83H. At that point the page address can no longer be continuously modified. For details, see
6.3 Column
Address Circuit
.
A0
E, /RD
R,/W, /WR
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
0
0
0
0
1
A7
A6
A5
A4
0
A3
A2
A1
A0
A7
A6
A5
A4
A3
A2
A1
A0
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
↓
↓
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
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