參數(shù)資料
型號： UPD161401
廠商： NEC Corp.
英文描述： 256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
中文描述： 256色，1/80-DUTY LCD控制器/驅(qū)動器，片內(nèi)RAM
文件頁數(shù)： 19/124頁
文件大?。?/td> 647K
代理商： UPD161401
Data Sheet S15726EJ2V0DS
19
μ
PD161401
5.1.3
Serial interface
When the serial interface has been selected (IFM1, IFM0 = L, L), as long as the chip is in an active state (/CS1= L,
CS2 = H ), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read in the order of D
7
, then
D
6
to D
0
at the rising edge of the serial clock input from the serial input pin. This data is converted to parallel data in
synchronization with the 8th rising edge of the serial clock. Serial input data is judged as display data/command data if
RS = H and an index if RS = L. The RS input is read every 8th rising edge of the serial clock after the chip becomes
active and is used for data discrimination.
Figure 5
1. Serial Interface Signal Chart
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
/CS1
SI
SCL
RS
CS2 = "H"
Remarks 1.
If the chip is not in an active state, the shift register and counter are reset to their initial statuses.
2.
The serial clock counter is reset by initialization from the /DISP pin.
3.
Data cannot be read when using serial interface mode.
4.
Care must be taken when performing SCL wiring to avoid effects from terminal radiation or external noise
caused by the wiring length. It is recommended to confirm operation using the actual equipment to be
used.
5.1.4
Chip select
The
μ
PD161401 has chip select pins (/CS1 and CS2). The CPU parallel interface or Serial interface can be used only
when /CS1 = L (CS2 = H).
If the chip select pins are not active, the D
0
to D
15
pins go into a high-impedance state, and the RS, /RD, and /WR pins
do not become active.
5.1.5
Accessing display data RAM and internal registers
When the CPU accesses the
μ
PD161401, the CPU only has to satisfy the requirement of the cycle time (t
CYC
) and can
transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.
When the CPU writes data to the
μ
PD161401, no dummy data is necessary. When reading data, dummy data is not
necessary either. In the
μ
PD161401, the data of the display access memory register, the complementary color blink
data memory register, the specified color blink data memory register and the reverse data memory access register
(R12, R41, R45, R50) cannot be read.
Figure 5
2
illustrates as follows.
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