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| 型號： | UPD161401 |
| 廠商： | NEC Corp. |
| 英文描述： | 256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 中文描述： | 256色，1/80-DUTY LCD控制器/驅(qū)動(dòng)器，片內(nèi)RAM |
| 文件頁數(shù)： | 13/124頁 |
| 文件大小： | 647K |
| 代理商： | UPD161401 |
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Data Sheet S15726EJ2V0DS
13
μ
PD161401
3.2 Logic Circuit Pins (1/3)
Symbol
Pin Name
Pin No.
I/O
Description
/CS1,
CS2
Chip select
98 to 100,
101 to 103
Input
These pins are chip select signal pins.
When /CS1 = L (CS2 = H), the chip is active, and data/command
can be input or output and I/O manipulated.
/RD (E)
Read (enable)
119 to 121
Input
When i80 system parallel data transfer is selected (/RD), read is
enabled by this signal. When this pin is L, data is output to the data
bus. When M68 system parallel data transfer is selected (E), this
pin inputs an enable signal that triggers data write or read.
But in the
μ
PD161401, the data of the display access memory
register, the complementary color blink data memory register, the
specified color blink data memory register and the reverse data
memory access register (R12, R41, R45, R50) cannot be read.
/WR (R,/W)
Write (read/write)
116 to 118
Input
When i80 system parallel data transfer is selected (/WR), write is
enabled by this signal. Data is written at the rising edge of this
signal. When M68 system parallel data transfer is selected (R, /W),
this pin determines the data transfer direction, as follows:
0: Write
1: Read
Selects an interface mode
IFM1
IFM0
Interface Mode
L
L
Serial
L
H
Setting prohibited
H
L
i80 series parallel
H
H
M68 series parallel
IFM0,
IFM1
Interface selection
86 to 88,
80 to 82
Input
D
0
to D
15
(SI)
(SCL)
Data bus
(serial input)
(serial clock)
187 to 182,
178 to 170,
166 to 158,
154 to 149,
145 to 137,
133 to 125
I/O
This is a bi-directional data bus connected to an 8- or 16-bit
standard CPU bus.
When the serial interface mode is selected (IFM1, IFM0 = L, L), D
7
functions as a serial data input pin (SI), and D
6
serves as a serial
clock input pin (SCL). At this time, D
0
to D
5
and D
8
to D
15
go into a
high-impedance state.
When the 8-bit data bus is selected, only D
0
to D
7
are used, and D
8
to D
15
go into a high-impedance state. Data is input starting from its
higher byte, followed by the lower byte. If the chip is not selected,
all D
0
to D
15
go into a high-impedance state.
This pin is usually connected to the least significant bit of a
standard CPU address bus to identify whether data is an index
register or data/command.
RS = H: Indicates that D
0
to D
15
are data/command.
RS = L: Indicates that D
0
to D
15
are an index register.
RS
Index register/data
command selection
110 to 112
Input
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