參數(shù)資料
型號(hào): uPC1853CT-01
廠商: NEC Corp.
英文描述: MATRIX SURROUND IC WITH I2C BUS
中文描述: 矩陣環(huán)繞集成電路I2C總線
文件頁數(shù): 20/76頁
文件大?。?/td> 544K
代理商: UPC1853CT-01
μ
PC1853
20
3.2.2 Serial data transfer
The following is the format in the case of transferring 8 bytes data at one time by using automatic increment function
(the data of subaddress 01H to 08H, bit D6 is “1”).
S
T
A
W
A
C
K
A
C
K
A
C
K
S
T
P
A
C
K
A
C
K
SLAVE
ADDRESS
SUB
ADDRESS
DATA1
DATA2
DATA9
Remark
STA: Start, W: Write mode, ACK: Acknowledge, STP: Stop
The master CPU transfers “00H” as subaddress SA
0
after start and slave address like above figure. It transfers
the data of SA
0
after subaddress, and then transfers the data of SA
1
, SA
2
..., SA
8
continuously without transferring
stop condition. Finally, it transfers stop condition and terminates.
The increments of the subaddress of the
μ
PC1853 stops automatically when the subaddress comes to “08H” inside
of it.
3.2.3 Acknowledge
On I
2
C bus, acknowledge bit is added to the 9th bit after the data in order to judge whether data transfer has been
succeeded or not. The master CPU judges it from “High” and “Low” of acknowledge condition.
When this acknowledge period is “Low”, it means success. And when the condition is “High”, it means failure of
transfer or forced release of bus as NAK state.
The condition of being NAK state is when wrong slave address is transferred to slave IC or data transfer from slave
side is finished in read state.
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