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1998
MOS FIELD EFFECT TRANSISTOR
μ
PA1755
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DATA SHEET
Document No.
Date Published
Printed in Japan
G12715EJ1V0DS00 (1st edition)
March 1999 NS CP(K)
PACKAGE DRAWING (Unit : mm)
1.27
0.12 M
6.0 ±0.3
4.4
0.40
+0.10
0.78 Max.
0
1
1
0.8
0.5 ±0.2
0
+
–
5.37 Max.
0.10
1
4
8
5
1
2
7, 8
3
4
5, 6
; Source 1
; Gate 1
; Drain 1
; Source 2
; Gate 2
; Drain 2
EQUIVALENT CIRCUIT
(1/2 Circuit)
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
DESCRIPTION
This product is Dual N-channel MOS Field Effect
Transistor designed for DC/DC converters and power
management applications of notebook computers.
FEATURES
Dual chip type
Low on-resistance
R
DS(on)1
= 32 m
MAX. (V
GS
= 10
V, I
D
= 3.5
A)
R
DS(on)2
= 45 m
MAX. (V
GS
= 4.5
V, I
D
= 3.5
A)
Low input capacitance C
iss
= 895
pF TYP.
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA1755G
Power SOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 °C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0)
V
DSS
30
V
Gate to Source Voltage (V
DS
= 0)
V
GSS
±
20
±
7.0
±
28
V
Drain Current (DC)
Drain Current (pulse)
Note1
Total Power Dissipation (1 unit)
Note2
Total Power Dissipation (2 unit)
Note2
I
D(DC)
A
I
D(pulse)
A
P
T
1.7
W
P
T
2.0
W
Channel Temperature
T
ch
150
°C
Storage Temperature
T
stg
–55 to + 150
°C
Notes 1.
PW
≤
10
μ
s, Duty cycle
≤
1 %
2.
T
A
= 25
°
C, Mounted on ceramic substrate of 2000 mm
2
x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.