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參數(shù)資料
| 型號(hào)： | UMA1018M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-voltage dual frequency synthesizer for radio telephones |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1250 MHz, PDSO20 |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | UMA1018M |
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1995 Jun 27
7
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
UMA1018M
Table 4
Fast and normal charge pumps current ratio (note 1)
Note
1.
; common bias current for charge pumps and DAC.
Table 5
Power-down modes
CR1
CR0
I
CPA
4
×
I
SET
4
×
I
SET
4
×
I
SET
4
×
I
SET
I
CPP
4
×
I
SET
4
×
I
SET
2
×
I
SET
2
×
I
SET
I
CPPF
16
×
I
SET
32
×
I
SET
24
×
I
SET
32
×
I
SET
I
CPPF
: I
CPP
4 : 1
8 : 1
12 : 1
16 : 1
0
0
1
1
0
1
0
1
AON
PON
FAST
PRINCIPAL
DIVIDERS
AUXILIARY
DIVIDERS
PUMP
CPA
PUMP
CPP
PUMP
CPPF
DAC AND BIAS
0
0
0
1
1
1
0
1
1
0
1
1
X
0
1
X
0
1
OFF
ON
ON
OFF
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
ON
ON
ON
ON
I
SET
V
ext
R
=
Digital-to-analog converter
The 7-bits loaded via the bus into the appropriate latch
drive a digital-to-analog converter. The internal current is
scaled by the external resistance (R
ext
) at pin I
SET
, similar
to the charge pumps. The nominal full-scale current is
2
×
I
SET
. The output current is mirrored to produce a
full-scale voltage into a user-defined ground referenced
resistance, thereby allowing optimum swing from power
supply rails within the 2.7 to 5.5 V limits. The band gap
reference voltage at pin I
SET
is temperature and supply
independent. The DAC signal is monotonic across the full
range of digital input codes to enable fine adjustment of
other system blocks. The typical settling time for full-scale
switching is 400 ns into a 12 k
// 20 pF load. DAC
functionality is neither tested nor guaranteed on
UMA1018M versions with the /S1 suffix.
Power-down modes
The action of the control inputs on the state of internal
blocks is defined by Table 5.
It should be noted that in Table 5, PON and AON can be
either the software or hardware power-down signals.
The dividers are ON when both hardware and software
power-down signals are at logic 1.
When either synthesizer is reactivated after power-down
the main and reference dividers of that synthesizer are
synchronized to avoid the possibility of random phase
errors on power-up.
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