參數(shù)資料
型號(hào): UMA1018M
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Low-voltage dual frequency synthesizer for radio telephones
中文描述: PLL FREQUENCY SYNTHESIZER, 1250 MHz, PDSO20
文件頁數(shù): 10/20頁
文件大小: 166K
代理商: UMA1018M
1995 Jun 27
10
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
UMA1018M
Auxiliary main divider input; pin 15
f
AI
V
15(rms)
input frequency
AC-coupled input signal level
(RMS value)
20
50
300
500
MHz
mV
R
s
= 50
;
2.7 V < V
DD
< 4.5 V;
T
amb
=
30 to +85
°
C
R
s
= 50
;
2.7 V < V
DD
< 5.5 V;
T
amb
=
20 to +85
°
C
f
AI
= 100 MHz
indicative, not tested
100
500
mV
Z
I
C
I
R
am
f
APCmax
input impedance (real part)
typical pin input capacitance
auxiliary main divider ratio
maximum auxiliary phase
comparator frequency
minimum auxiliary phase
comparator frequency
64
1
2
2000
16383
k
pF
kHz
f
APCmin
10
kHz
Crystal reference divider input; pin 8
f
XTAL
V
8(rms)
crystal reference input frequency
sinusoidal input signal level
(RMS value)
5
50
50
8
8
6
2
40
500
250
2047
2047
MHz
mV
mV
k
pF
4.0 V < V
DD
< 5.5 V
2.7 V < V
DD
< 5.5 V
f
XTAL
= 30 MHz
indicative, not tested
Z
I
C
I
R
pr
R
ar
input impedance (real part)
typical pin input capacitance
principal reference divider ratio
auxiliary reference divider ratio
Charge pump current setting resistor input; pin 14
R
ext
external resistor from pin 14 to
ground
regulated voltage at pin 14
12
60
k
V
14
Charge pump outputs; pins 17, 3 and 2; R
ext
= 12 k
I
Ocp
charge pump output current error
I
match
sink-to-source current matching
I
Lcp
charge pump off leakage current
V
cp
charge pump voltage compliance
R
ext
= 12 k
1.15
V
25
5
0.4
±
5
±
1
+25
+5
V
CC
0.4
%
%
nA
V
V
cp
in range
V
cp
=
1
2
V
CC
Interface logic input signal levels; pins 13, 12, 11 and 1
V
IH
V
IL
I
bias
C
I
HIGH level input voltage
LOW level input voltage
input bias current
input capacitance
0.7V
DD
0.3
5
2
V
DD
+ 0.3 V
0.3V
DD
+5
V
μ
A
pF
logic 1 or logic 0
indicative, not tested
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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