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參數(shù)資料
| 型號： | UMA1015AM |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-power dual frequency synthesizer for radio communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 159K |
| 代理商： | UMA1015AM |
1997 Sep 03
9
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
RF main divider input; RFA and RFB
f
RF
V
RF(rms)
RF input frequency
RF input signal voltage
(RMS value; AC coupled)
50
50
1100
250
MHz
mV
R
s
= 50
;
f
RF
= 400 to 1100 MHz
R
s
= 50
;
f
RF
= 80 to 400 MHz 150
R
s
= 50
;
f
RF
= 50 to 80 MHz
f
RF
= 1 GHz; indicative, not
tested
indicative, not tested
300
400
400
mV
mV
225
Z
I
input impedance
(real part)
input capacitance
principle main divider ratio
C
I
R
pm
512
1
131071
pF
Reference divider input; f
XTALIN
f
XTALIN
reference input frequency
from crystal
3
35
MHz
V
XTALIN(rms)
sinusoidal input voltage
(RMS value)
Z
I
input impedance
(real part)
C
I
input capacitance
R
rd
reference divider ratio
100
500
mV
f
XTALIN
= 12.8 MHz; indicative,
not tested
indicative, not tested
10
k
8
1
4095
pF
Charge pump current setting resistor input; I
SET
V
SET
voltage output on I
SET
R
SET
= 12 to 60 k
1.1
V
Charge pump outputs; CPA and CPB
I
cp
charge pump sink or
source current
R
SET
= 15 k
;
CRA/CRB = logic 1;
I
cp
= I
SET
×
24;
V
cp
= 0.4 V to V
CC
0.5 V
R
SET
= 15 k
;
CRA/CRB = logic 0;
I
cp
= I
SET
×
12;
V
cp
= 0.4 V to V
CC
0.5 V
V
cp
= 0.4 V to V
CC
0.5 V
1.3
1.75
2.3
mA
0.7
0.9
1.2
mA
I
LI
charge pump off leakage
current
5
±
1
+5
nA
Logic input signal levels; DATA, CLK, E and HPD
V
IH
V
IL
I
bias
C
I
HIGH level input voltage
LOW level input voltage
input bias currents
input capacitance
at logic 1
at logic 0
at logic 1 or logic 0
indicative, not tested
0.7V
DD1
0.3
5
V
DD1
+ 0.3
0.3V
DD1
+5
V
V
μ
A
pF
1
Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and f
XTALO
- open drain outputs
V
OL
LOW level output voltage
I
sink
< 0.4 mA
0.4
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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