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參數(shù)資料
| 型號： | UMA1015AM |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-power dual frequency synthesizer for radio communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 159K |
| 代理商： | UMA1015AM |
1997 Sep 03
4
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015AM
PINNING
SYMBOL
PIN
DESCRIPTION
P1
P2
CPA
V
DD1
HPD
1
2
3
4
5
output Port 1
output Port 2
charge pump output synthesizer A
digital supply voltage 1
hardware power-down
(input LOW = power-down)
RF input synthesizer A
digital ground
common crystal frequency input from
TCXO
output Port 3
open-drain output of f
XTAL
signal
programming bus clock input
programming bus data input
programming bus enable input
(active LOW)
digital supply voltage 2
RF input synthesizer B
analog ground to charge pumps
charge pump output synthesizer B
analog supply to charge pump;
external or voltage doubler output
Port output 0/out-of-lock output
regulator pin to set charge pump
currents
RFA
DGND
f
XTALIN
6
7
8
P3
f
XTALO
CLK
DATA
E
9
10
11
12
13
V
DD2
RFB
AGND
CPB
V
CC
14
15
16
17
18
P0/OOL
I
SET
19
20
Fig.2 Pin configuration.
handbook, halfpage
P1
P2
CPA
VDD1
HPD
RFA
DGND
fXTALIN
P3
fXTALO
ISET
P0/OOL
VCC
CPB
RFB
VDD2
AGND
E
DATA
CLK
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
UMA1015AM
MGG522
FUNCTIONAL DESCRIPTION
Main dividers
Each synthesizer has a fully programmable 17-bit main
divider. The RF input drives a pre-amplifier to provide the
clock to the first divider bit. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from below
50 mV (RMS) up to 250 mV (RMS), and at frequencies up
to 1.1 GHz. The high frequency sections of the divider are
implemented using bipolar transistors, while the slower
section uses CMOS technology. The range of division
ratios is 512 to 131071.
Reference divider
There is a common fully programmable 12-bit reference
divider for the two synthesizers. The input f
XTALIN
drives a
pre-amplifier to provide the clock input for the reference
divider. This clock signal is also inverted and output on pin
f
XTALO
(open drain). A crystal connected between f
XTALIN
and f
XTALO
with suitable feedback components can be
used to make an oscillator. An extra divide-by-2 block
allows a reference comparison frequency for
synthesizer B to be half the frequency of synthesizer A.
This feature is selectable using the program bit SR. If the
programmed reference divider ratio is R then the ratio for
each synthesizer is as given in Table 1.
The range for the division ratio R is 8 to 4095. Opposite
edges of the divider output are used to drive the phase
detectors to ensure that active edges arrive at the phase
detectors of each synthesizer at different times. This
minimizes the potential for interference between the
charge pumps of each loop. The reference divider consists
of CMOS devices operating beyond 35 MHz.
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| UMA1015M | Low-power dual frequency synthesizer for radio communications |
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相關(guān)代理商/技術(shù)參數(shù) |
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| UMA1015M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power dual frequency synthesizer for radio communications |
| UMA1015M/C2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power dual frequency synthesizer for radio communications |
| UMA1016AT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Frequency synthesizer for radio communication equipment |
| UMA1016BT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Frequency synthesizer for radio communication equipment |
| UMA1016XT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial-Input Frequency Synthesizer |
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