參數(shù)資料
型號: UDA1361TS/N1,112
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 96 kHz sampling 24-bit stereo audio ADC; Package: SOT369-1 (SSOP16); Container: Tube
中文描述: 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 4.40 MM, PLASTIC, SOT369-1, SSOP-16
文件頁數(shù): 17/20頁
文件大?。?/td> 100K
代理商: UDA1361TS/N1,112
2002 Nov 25
6
Philips Semiconductors
Product specication
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
Table 4
Decimation lter characteristic
DC cancellation lter
A IIR high-pass filter is provided to remove unwanted
DC components. The filter characteristics are given in
Table 5.
Table 5
DC cancellation lter characteristic
Mute
On recovery from Power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:
, t = 256 ms when fs = 48 kHz.
Power-down mode/input voltage control
The PWON pin can control the power saving together with
the optional gain switch for 2 or 1 V (RMS) input.
The UDA1361TS supports 2 V (RMS) input using a series
resistor of 12 k
. For the definition of the pin settings for
1 or 2 V (RMS) mode, it is assumed that this resistor is
present as a default component.
Table 6
Power-down/input voltage control
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
0 to 0.45fs
±0.01
Pass-band droop
0.45fs
0.2
Stop band
>0.55 fs
70
Dynamic range
0 to 0.45 fs
>135
ITEM
CONDITION
VALUE (dB)
Pass-band ripple
none
Pass-band gain
0
Droop
at 0.00045fs
0.031
Attenuation
at DC
at 0.00000036fs
>40
Dynamic range
0 to 0.45fs
>135
PWON
POWER-DOWN OR GAIN
L
Power-down mode
M
0 dB gain
H
6 dB gain
t
12288
f
s
----------------
=
Serial interface formats
handbook, full pagewidth
MGT453
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
3
2
1
3
2
1
MSB
B2
MSB
LSB
MSB
B2
≥8
BCK
DATA
WS
LEFT
RIGHT
3
2
1
3
2
1
MSB
B2
MSB
LSB
MSB
B2
≥8
BCK
DATA
INPUT FORMAT I2S-BUS
Fig.3 Serial interface formats.
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