參數(shù)資料
型號(hào): UDA1351H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: 96 kHz IEC 958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 23/36頁
文件大小: 157K
代理商: UDA1351H
2000 Feb 18
23
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
8.7.8.13
Auto mute
A 1-bit value to activate mute during out-of-lock. In normal
operation the output is automatically hard muted when an
out-of-lock situation is detected. Setting this bit to logic 0
will disable that function.
Table 21
Auto mute setting
8.7.8.14
PLL reset
A 1-bit value to reset the PLL. This is the bit which is set in
the initialization string. When this bit is asserted, the PLL
will be reset and the output clock of the PLL will be forced
to its lowest value, which is in the area of a few MHz.
Table 22
PLL reset
8.7.9
R
EADABLE REGISTERS
8.7.9.1
Mute status
A 1-bit value indicating whether the interpolator is muting
or not muting.
Table 23
Interpolator mute status
8.7.9.2
PLL lock detection
A 1-bit value indicating that the clock regeneration is
locked.
Table 24
PLL lock indication
8.7.9.3
SPDIF lock detection
A 1-bit value indicating the IEC 958 decoder is locked and
is decoding correct data.
Table 25
SPDIF lock detection
8.7.9.4
Audio sample frequency detection
A 2-bit value indicating the audio sample frequency of the
IEC 958 input signal.
Table 26
Audio sample frequency detection
Auto MT
FUNCTION
0
1
do not mute output during out-of-lock
mute output during out-of-lock (default
setting)
RST PLL
FUNCTION
0
1
normal operation (default)
PLL is reset
MT stat
FUNCTION
0
1
no muting
muting
PLL lock
FUNCTION
0
1
out-of-lock
locked
SPD lock
FUNCTION
0
1
not locked
or
non-PCM data detected
locked
and
PCM data detected
ASF1
ASF0
FUNCTION
0
0
1
1
0
1
0
1
44.1 kHz
undefined
48.0 kHz
32.0 kHz
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