參數(shù)資料
型號: UDA1351H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: 96 kHz IEC 958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 11/36頁
文件大小: 157K
代理商: UDA1351H
2000 Feb 18
11
Philips Semiconductors
Preliminary specification
96 kHz IEC 958 audio DAC
UDA1351H
8.4
Auto mute
By default the outputs of the digital data output interface
and the DAC will be muted until the IC is locked,
regardless the level on pin MUTE (in static mode) or the
state of bit MT of the sound feature register (in L3 mode).
In this way only valid data will be passed to the outputs.
This mute is done in the SPDIF interface and is a hard
mute, not a cosine roll-off mute.
If needed this muting can be bypassed by setting
bit AutoMTtologic 0viatheL3 interface.Asaresultthe IC
will no longer mute during out-of-lock situations.
8.5
Data path
The UDA1351H data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.5.1
IEC 958
INPUT
The UDA1351H IEC 958 decoder can select 1 out of 2
IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.4).
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
The extracted key parameters are:
Pre-emphasis
Audio sample frequency
Two-channel PCM indicator
Clock accuracy.
Both the lock indicator and the key channel status bits are
accessible via the L3 interface.
The UDA1351H supports the following sample
frequencies and data bit rates:
f
s
= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
f
s
= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
f
s
= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s
f
s
= 64.0 kHz, resulting in a data rate of 4.096 Mbits/s
f
s
= 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s
f
s
= 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.
The UDA1351H supports timing level I, II and III as
specified by the IEC 958 standard.
handbook, halfpage
MGL975
15,
16
SPDIF0,
SPDIF1
75
180 pF
10 nF
UDA1351H
Fig.4 IEC 958 input circuit and typical application.
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