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| 型號： | TVP5158PNPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | GREEN, PLASTIC, HTQFP-128 |
| 文件頁數(shù)： | 40/108頁 |
| 文件大?。?/td> | 1395K |
| 代理商： | TVP5158PNPR |
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SLES243E
– JULY 2009 – REVISED MARCH 2011
Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are
high. The slave address select terminals (I2CA0, I2CA1 and I2CA2) enable the use of up to eight devices
on the same I2C bus. At the trailing edge of reset, the status of the I2CA0, I2CA1 and I2CA2 lines are
sampled to determine the device address used. Table 3-16 summarizes the terminal functions of the I2C
host interface. Table 3-17 shows the device address selection options.
Table 3-16. I2C Terminal Description
SIGNAL
TYPE
DESCRIPTION
I2CA0
I
Slave address selection
I2CA1
I
Slave address selection
I2CA2
I
Slave address selection
SCL
I/O (open drain)
Input/output clock line
SDA
I/O (open drain)
Input/output data line
Table 3-17. I2C Host Interface Device Addresses
A6
A5
A4
A3
A2(I2CA2)
A1(I2CA1)
A0 (I2CA0)
R/W
HEX
1
0
1
0
1/0
B1/B0
1
0
1
0
1
1/0
B3/B2
1
0
1
0
1
0
1/0
B5/B4
1
0
1
0
1
1/0
B7/B6
1
0
1
0
1/0
B9/B8
1
0
1
0
1
1/0
BB/BA
1
0
1
0
1/0
BD/BC
1
0
1
1/0
BF/BE
Data transfer rate on the bus is up to 400 kbit/s. The number of devices connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
To simplify programming of each of the 4 decoder channels a single I2C write transaction can be
transmitted to any one or more of the 4 cores in parallel. This reduces the time required to download
firmware or to configure the device when all channels are to be configured in the same manner. It also
enables the addresses for all registers to be common across all decoders.
I2C sub-address FEh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder
write enable bit is set, then I2C write transactions will be sent to the corresponding decoder core. For
multi-byte I2C write transactions there are options to auto-increment the sub-address or to auto-increment
through the selected decoders or both.
I2C sub-address FFh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder
read enable bit is set, then I2C read transactions will be sent to the corresponding decoder core.
If more than one decoder is enabled for reads then the lowest numbered decoder that is enabled will
respond to the read transaction. For multi-byte I2C read transactions there are options to auto-increment
the sub-address or to auto-increment through the selected decoders or both.
Copyright
2009–2011, Texas Instruments Incorporated
Functional Description
37
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