SLES243E
– JULY 2009 – REVISED MARCH 2011
List of Figures
1-1
Functional Block Diagram
.......................................................................................................
123-1
Video Analog Processing and ADC Block Diagram
.........................................................................
163-2
Anti-Aliasing Filter Frequency Response
.....................................................................................
173-3
Composite Processor Block Diagram
..........................................................................................
183-4
Color Low-Pass Filter Frequency Response
.................................................................................
193-5
Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling
.................................
193-6
Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling
..............................................
203-7
Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling
................................................
203-8
Luminance Edge-Enhancer Peaking Block Diagram
........................................................................
213-9
Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling
............................................................
213-10
2-Ch Pixel-Interleaved Mode Timing Diagram
................................................................................
243-11
4-Ch Pixel-Interleaved Mode Timing Diagram
................................................................................
253-12
Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview
...............................................
283-13
Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview
...........................................
283-14
Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview
.....................................
293-15
Start Code in 8-Bit BT.656 Interface
...........................................................................................
303-16
Start Code in 16-Bit YCbCr 4:2:2 Interface
...................................................................................
303-17
Audio Sub-System Functional Diagram
.......................................................................................
333-18
Serial Audio Interface Timing Diagram
........................................................................................
343-19
Audio Cascade Connection
.....................................................................................................
353-20
VBUS Access
.....................................................................................................................
403-21
Clock and Crystal Connectivity
.................................................................................................
413-22
Reset Timing
......................................................................................................................
425-1
Video Output Clock and Data Timing
..........................................................................................
935-2
I
2C Host Port Timing
.............................................................................................................
946-1
4-Ch D1 Application (Single BT.656 Interface)
...............................................................................
966-2
4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface)
.........................................................................
966-3
8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application
.....................................................
976-4
8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application
.....................................................
976-5
Video Input Connectivity
.........................................................................................................
996-6
Audio Input Connectivity
.........................................................................................................
994
List of Figures
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2009–2011, Texas Instruments Incorporated