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參數(shù)資料
| 型號(hào)： | TVP5150AM1PBSRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP32 |
| 封裝： | PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 16/77頁 |
| 文件大?。?/td> | 291K |
| 代理商： | TVP5150AM1PBSRG4 |
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2.15.2.2 Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Step 11
9
I2C Not acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
2.15.2.3 I2C Timing Requirements
The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In
accordance with I2C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait
period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h8Fh (addresses 90hFFh do not require delays)
Start
Slave address
(B8h)
Ack
Subaddress
Ack
Data
(XXh)
Ack
Wait 64
s
Stop
The 64-
s delay is for all registers that do not require a reinitialization. Delays may be more for some registers.
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 25 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
CL1 = CL2 = 2CL CSTRAY,
where CSTRAY is the terminal capacitance with respect to ground. Figure 25 shows the reference clock
configurations.
TVP5150A
5
XTAL1
14.31818-MHz
Crystal
6
XTAL2
TVP5150A
5
XTAL1
6
XTAL2
CL1
CL2
14.31818-MHz
TTL Clock
Figure 25. Reference Clock Configurations
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| TVP5150AZQC | COLOR SIGNAL DECODER, PBGA48 |
| TVP5150APBSRG4 | COLOR SIGNAL DECODER, PQFP32 |
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| TVP5150AM1ZQC | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Vid Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150AM1ZQCR | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Vid Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150APBS | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Vid Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150APBSR | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Vid Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5150APBSRG4 | 功能描述:視頻 IC Ultralo Pwr NTSC/PAL SECAM Video Decoder RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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