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參數(shù)資料
| 型號： | TVP5040PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 88/101頁 |
| 文件大小： | 464K |
| 代理商： | TVP5040PFP |
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2–71
CC Even Field
*0 = Buffer empty
1 = Even field closed caption buffer contains data
CC Odd Field
*0 = Buffer empty
1 = Odd field closed caption buffer contains data
Bus Error
*0 = No bus error
1 = PHI interface detected an illegal access
Cycle Complete
*0 = Read or write cycle in progress
1 = Read or write cycle complete
tvpLOCK Interrupt
*0 = A transition has not occurred on the tvpLOCK signal
1 = A transition has occurred on the tvpLOCK signal
Note, an interrupt will be generated on any transition of the Lock signal.
tvpLOCK State
*0 = TVP not locked to video
1 = TVP locked to video signal
Reflects the present state of the tvpLOCK.
The interrupt status register A is polled by the external processor to determine the interrupt source. After an interrupt
condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
2.13.62 Interrupt Enable Register A
VIP address
1C1h
PHI address
C1h
I2C address
C1h
7
6
5
4
3
2
1
0
tvpLOCK state
tvpLOCK
interrupt
enable
Cycle complete
enable
Bus Error
Enable
CC odd field
enable
CC even field
enable
Teletext
threshold
enable
Teletext data
enable
The interrupt enable register A is used by the external processor to mask unnecessary interrupt sources for interrupt
A. Bits loaded with a 1 will allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely bits loaded with a 0 will mask the corresponding interrupt condition from generating an interrupt on the
external pin. Note this register only affects the interrupt A on the external terminal, it does not affect the bits in the
interrupt status register A. A given condition can set the appropriate bit in the status register and not cause an interrupt
on the external terminal. To determine if this device is driving the interrupt terminal either perform a logical AND of
the interrupt status register A with the interrupt enable register A, or check the state of the interrupt A bit in the interrupt
configuration register A.
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