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參數(shù)資料
| 型號： | TVP5040PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 30/101頁 |
| 文件大?。?/td> | 464K |
| 代理商： | TVP5040PFP |
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2–18
9
ACK
8
DATA
9
ACK
1-7
DATA
VC0(SCL)
P
Stop Condition
8
DATA
9
ACK
1-7
DATA
8
RW
1-7
ADDRESS
S
Start Condition
VC0(SCL)
VC1(SDA)
Figure 2–27. I2C Data Transfer
The data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent
on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the clock.
The high or low state of the data line can only change with the clock signal on the SCL line being low.
If multiple bytes are transferred during one read or write operation, the internal subaddress is automatically
incremented.
A high to low transition on the SDA line while the SCL is high indicates a start condition.
A low to high transition on the SDA line while the SCL is high indicates a stop condition.
Acknowledge (SDA low)
Not-Acknowledge (SDA high)
Every byte placed on the SDA line must be 8-bits long. The number of bytes that can be transferred is unrestricted.
Each byte must be followed by an acknowledge bit. If the slave can not receive another complete byte of data until
it has performed another function, it can hold the clock line (SCL) low to force the master into a wait state. Data transfer
then continues when the slave is ready for another byte of data and releases the clock line (SCL).
The data transfer with acknowledgement is obligatory. The acknowledge related clock pulse is generated by the
master. The master releases the SDA line high during the acknowledge clock pulse. The slave must pull down the
SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse.
When a slave does not acknowledge the slave address, the data line must be left high by the slave. The master can
then generate a stop condition to abort the transfer.
If a slave does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes,
the master must again abort the transfer. This is indicated by the slave generating the not acknowledge on the first
byte to follow. The slave leaves the data line high and the master generates the STOP condition.
If a master-receiver is involved in a transfer, it must signal the end of the data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter must release the data line
to allow the master to generate a stop or repeated start condition.
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