vii
List of Illustrations
Figure
Title
Page
2–1 Analog Video Processors and A/D Converters
2–1
. . . . . . . . . . . . . . . . . . . . . . . .
2–2 Digital Video Signal Processing Block Diagram
2–3
. . . . . . . . . . . . . . . . . . . . . . .
2–3 Digital Input Multiplexer
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 Decimation Filter Frequency Response
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Y/C Separation Block Diagram
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Color Low-Pass Filter Frequency Response
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Color Low-Pass Filter With Notch Filter Frequency Response
(NTSC And PAL-M Square Pixel Sampling)
2–6
. . . . . . . . . . . . . . . . . . . . . . . .
2–8 Color Low-Pass Filter With Notch Filter Characteristics
(13.5 MHz Sampling)
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Color Low-Pass Filter With Notch Filter Frequency Response
(PAL Square Pixel Sampling)
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 3-Line Adaptive Comb Filtering
2–7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 Comb Filters Frequency Response
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Chroma Trap Filter Frequency Response
(NTSC Square Pixel Sampling)
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13 Chroma Trap Filter Frequency Response (13.5 MHz Sampling)
2–8
. . . . . . . .
2–14 Chroma Trap Filter Frequency Response
(PAL Square Pixel Sampling)
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–15 Luminance Edge-Enhancer Peaking Block Diagram
2–9
. . . . . . . . . . . . . . . . . .
2–16 Peaking Filter Response, NTSC and PAL-M Square Pixel Sampling
2–9
. . . .
2–17 Peaking Filter Response, 13.5 MHz Sampling Rate
2–9
. . . . . . . . . . . . . . . . . .
2–18 Peaking Filter Response, PAL Square Pixel
2–10
. . . . . . . . . . . . . . . . . . . . . . . . .
2–19 Clock Circuit Diagram
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–20 Example Reference Clock Configurations
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–21 GLCO Timing
2–12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–22 4:2:2 Sampling
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–23 20-Bit 4:2:2 Output Format
2–13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–24 20-Bit 4:2:2 Output Format
2–14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–25 Vertical Synchronization Signals
2–15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–26 Horizontal Synchronization Signals
2–16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–27 I2C Data Transfer
2–18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–28 VIP Transfer
2–25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–29 Reading From Registers With Wait States
2–28
. . . . . . . . . . . . . . . . . . . . . . . . . . .