參數(shù)資料
型號(hào): TVP5040CPFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 54/109頁
文件大?。?/td> 568K
代理商: TVP5040CPFP
2–33
2.8.7
Parallel Host Interface A
Parallel host interface A is compatible with the video module interface (VMI) proposal version 1.4 mode A. The
terminal descriptions are defined in Table 2–7.
Table 2–7. Parallel Host Interface A Terminal Description
TERMINAL
SIGNAL
TYPE
DESCRIPTION
A[1:0]
HA[1:0]
I
Address bus from host
D[7:0]
HD[7:0]
I/O
Bidirectional data bus
VC3
CS
I
Chip select, active low
VC2
DS
I
Data strobe, active low
VC1
RD/WR
I
Read, active high — Write, active low
VC0
DTACK
O
Data acknowledge
INTREQ
O
Interrupt request, active low and open drain by default, an external pullup resistor is required—can be
configured as a conventional CMOS buffer, active high with no external pullup resistor.
Parallel host interface A timing is shown in the Figure 2–33. The cycle is initiated by the host when VC2-DS transitions
low. The TVP5040 responds by pulling VC0-DTACK low to indicate data has been received or that the requested data
is present on the bus. The host then completes the cycle by pulling VC2-DS high. Once the host has completed the
cycle, the TVP5040 sets VC0-DTACK to high impedance. A pullup is required to pull VC0-DTACK high to indicate
the operation is complete.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(1)
A[1:0],D[0:7], RD/WR setup until DS low
5
ns
td(1)
Delay DTACK low after DS low
0
ns
th(1)
A[1:0], D[0:7], RD/WR hold after DS high
5
ns
td(2)
Delay DS high after DTACK low
5
ns
td(3)
Delay DTACK high after DS high
0
ns
td(4)
Delay DS low(next cycle) after DTACK high
5
ns
tsu(2)
(Read cycle) D[7:0] setup until DTACK low
10
ns
th(2)
(Read cycle) D[7:0] hold after DS high
0
ns
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