參數(shù)資料
型號(hào): TVP5040CPFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù): 4/109頁(yè)
文件大?。?/td> 568K
代理商: TVP5040CPFP
4–1
4 Application Information
4.1
Microcode Download
The TVP5040 has an internal processor and an associated 5Kx20 instruction RAM. The microprocessor controls
many of the device functions including PLL operation, AGC, sync, and register configuration. This programmable
architecture allows the TVP5040 performance to be enhanced with upgraded algorithms. The microcode for the
internal processor is downloaded to the TVP5040 during each power-up as described later.
The details of downloading the microcode depends on the host interface being used (I2C, VIP, or PHI).
4.1.1
Timing Requirement for Start of Download
Following the negation of the reset signal (RSTINB asserted high), the microcode instructions may be downloaded
after at least 4 pixel clock (PCLK) cycles have elapsed. Note that this time period is longer if the TVP5040 has not
already been initialized.
4.1.2
General Microcode Download Procedure
In general, the procedure is initiated by addressing the program RAM write register (address 7Eh) for a write
operation. After this the internal microprocessor is disabled and the internal microcode RAM is ready for microcode
download. The first instruction byte and subsequent instruction bytes written to the program RAM write register are
loaded to sequential locations of the microcode RAM. Each 20-bit instruction is transmitted using three bytes, with
the most significant byte first. Since the microcode RAM is 20-bits wide, the upper four bits of the most significant
byte are discarded before the data is written to the microcode RAM.
It is possible to complete the microcode download in a single burst of consecutive write cycle. If needed, the data may
be transmitted in separate blocks, so long as no other TVP5040 register (other than address 7Eh) is accessed in
between blocks. If another TVP5040 register is accessed, the microprocessor internal instruction RAM address
pointer is reset to zero and resumes operation.
4.1.3
Microprocessor Restart Operation
As noted before, the internal microprocessor unit is disabled during microcode download. Therefore, after completion
of the microcode download (that is, all microcode instructions have been written to the program RAM), a write cycle
to a register 7Fh is required to wake up the microprocessor and restart normal operation of the TVP5040.
4.1.3.1 Timing Requirement fort Microprocessor Restart
After the microprocessor-restart operation has been initiated, the microprocessor takes up to 5 ms for its initialization
code to complete. Only then register initialization via the host port begin. The following sections describe how this
latency is handled for the different host interfaces.
4.1.3.2 Implementation for I2C Bus
After the restart operation has been performed, the TVP5040 drives the I2C clock (SCL) low to signal the I2C master
to wait I2C implementation vary in the way this is handled. A problem arises when the I2C master tries to generate
STOP condition without checking if the I2C bus is free (that is, SCL high). This attempted-STOP condition is not
recognized by the I2C slave. The master then stops for a software-generated delay to meet the timing requirement
mentioned in Section 4.1.3.1. Finally, the I2C master resumes operation by generating a START condition. Since no
STOP condition was recognized by the slave, this is seen as a RESTART condition, which the TVP5040 does not
support.
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