參數(shù)資料
型號(hào): TVP5031PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù): 5/92頁(yè)
文件大?。?/td> 415K
代理商: TVP5031PFP
1–5
1.6
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
Analog Video
VI_1A
VI_1B
5
4
I
Analog video inputs. Up to two composite inputs. The inputs must be ac-coupled. The recommended coupling
is 0.1
F
Clock Signals
PCLK
27
O
Pixel clock output. The frequency is 12.2727 MHz for square-pixel NTSC, 14.75 MHz for square-pixel PAL,
and 13.5 MHz for ITU-R.BT.601 sampling modes.
PREF
26
I/O
Clock phase reference signal. This signal qualifies clock edges when SCLK is used to clock data that is
changing at the pixel clock rate.
SCLK
25
O
System clock output with twice the frequency of the pixel clock (PCLK).
XTAL1
XTAL2
35
36
I
External clock reference. The user may connect XTAL1 to a TTL-compatible oscillator or to one terminal of
a crystal oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818 MHz crystal or oscillator is needed for square pixel sampling and ITU-R
BT.601 sampling.
Digital Video
UV[9:0]
62, 61,
60, 59,
58, 56,
55, 53,
52, 51
I/O
10-bit digital chrominance outputs
Y[9:0]
50, 49,
48, 46,
45, 43,
42, 41,
40, 39
I/O
10-bit digital luminance outputs, or 10-bit multiplexed luminance and chrominance outputs. These terminals
may also be configured to output the data from the channel 1 A/D converter.
Host Port-Bus
A[1:0]
74, 73
I
PHI mode: PHI address port
D[7:0]
72, 71,
70, 69,
67, 66,
64, 63
I/O
PHI mode: PHI data port-bit [7:0]
INTREQ
80
I/O
PHI mode: Interrupt request (INTREQ). Pullup is required if configured as open drain.
I2C mode: Interrupt request (INTREQ). Pullup is required if configured as open drain.
VC0
79
I/O
PHI mode: PHI port data acknowledgement or ready signal (DTACK)
I2C mode: Serial clock (SCL) pullup is required.
VC1
78
I/O
PHI mode: PHI port read-write or write (RW/WR)
I2C mode: Serial data (SDA) pullup is required.
VC2
77
I/O
PHI mode: PHI port data strobe or read signal (DS/RD)
VC3
76
I
PHI mode: PHI port chip select (VC)
I2C mode: Slave address select (I2CA)
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