![](http://datasheet.mmic.net.cn/140000/TVP5020_datasheet_5023353/TVP5020_45.png)
2–31
VBI FIFO:
The VBI FIFO containing sliced VBI data is directly readable by the VMI host.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read VBI FIFO
1
0
Data from FIFO
Status/Interrupt Register:
The status/interrupt register provides the host with information containing the source of an interrupt. After
an interrupt condition is set, the condition can be reset by writing a one to the appropriate bit in the
status/interrupt register.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Access status/interrupt register
1
Data to/from status/interrupt register
2.11.2
VMI Microcode Write Operation
Data written to indirect register 7E will be written to the TVP5020 program RAM. During the address write
cycle the microprocessor resets and points to location zero in the program and remains reset. The
microprocessor requires a clear-reset operation upon completion of the write operation. The host performs
the reset by writing into the 7F register to clear reset and resume microprocessor function. (There is no
specific data to be written into the 7F register; any data will resume microprocessor function).
To avoid violating VMI cycle time requirements during microcode write operation, the host can poll the cycle
complete bit in the VMI status register after writing each byte of data to the VMI data register. Alternatively,
the cycle complete enable bit in the interrupt enable register (indirect address C1) can be set to generate
an interrupt for the host when a write operation is complete.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register address
0
1
0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register data
Write microcode
Register Data
Write microcode
Register data
0
1
First byte of microcode data
(Wait for cycle complete status or interrupt)
Second Byte of microcode data
(Wait for cycle complete status or interrupt)
Last byte of microcode data
(Wait for cycle complete status or interrupt)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Register address
0
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Dummy data
0
1
X