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1 Introduction
The TVP3030 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPIC
0.8-micron CMOS process. The TVP3030 is a 128-bit VIP that provides virtually all features of the 64-bit
TVP3026. The TVP3030 doubles the pixel bus bandwidth, enabling 24-bit/pixel displays at resolutions up
to 1600
×
1280 at a 76-Hz refresh rate. Also, 24-bit/pixel graphics at 1280
×
1024 resolution may be
implemented at higher refresh rates with or without the use of pixel packing.
With the wider pixel bus comes additional 24-bit/pixel multiplexing modes: 4:1 (128-bit bus width for overlay
and RGB) and 5:1 (120-bit bus width for RGB). The byte router function allows pseudo-color or monochrome
image data to be taken from the red, green, or blue color channels. This enables high performance
24-bit/pixel architectures organized as red, green, and blue memory banks to provide 8-bit/pixel modes as
well.
The TVP3030 extends the packed-24 modes to include 16:3 (pixels:load clocks) using a 128-bit pixel bus
width. This enables, for example, 24-bit/pixel graphics at 220 MHz pixel rate with only a 40 MHz VRAM serial
output. With the 8:3 packed-24 mode (64-bit pixel bus width), a 24-bit/pixel display with 1280 x 1024
resolution may be packed into 4 megabytes of VRAM. A PLL-generated, 50 % duty cycle reference clock
is output in the packed-24 modes, maximizing VRAM cycle time.
The TVP3030 supports all of the pixel formats of the TVP3026 VIP. Data can be split into 4 or 8 bit planes
for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct
color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured
to IBM XGA
(5, 6, 5), TARGA
(5, 5, 5, 1), or (6, 6, 4) as another existing format. An additional 12-bit mode
(4, 4, 4, 4) is supported with 4 bits for each color and overlay. All color modes support selection of little or
big endian data format for the pixel bus. Additionally, the device is also software compatible with the
IMSG176/8 and Bt476/8 color palettes.
Two fully programmable PLLs for pixel clock and memory clock functions are provided for dramatic
improvements in graphics system cost and integration. A third loop clock PLL is incorporated making pixel
data latch timing much simpler than with other existing color palettes. In addition, an external digital clock
input is provided for VGA modes. The reference clock output is driven by the loop clock PLL and provides
a timing reference to the graphics accelerator. The shift clock output may be used directly as the VRAM shift
clock.
Like the TVP3026, the TVP3030 also integrates a complete, IBM XGA-compatible hardware cursor on chip,
making significant graphics performance enhancements possible. Additionally, color-keyed switching is
provided, giving the user an efficient means of combining graphic overlays and direct-color images
on-screen.
The TVP3030 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters
(DACs) capable of directly driving a doubly terminated 75-
line. The lookup tables are designed with a
dual-ported RAM architecture that enables ultra-high speed operation.
The device features a separate VGA bus which supports the integrated VGA modes in graphics accelerator
applications, allowing efficient support for VGA graphics and text modes. The separate bus is also useful
for accepting data from the feature connector of most VGA supported personal computers, without the need
for external data multiplexing.
EPIC is a trademark of Texas Instruments Incorporated.
XGA is a registered trademark of IBM.
TARGA is a registered trademark of Truevision Incorporated.