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參數(shù)資料
| 型號(hào)： | TVP3030-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 25/107頁 |
| 文件大小： | 689K |
| 代理商： | TVP3030-175 |
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2–9
Table 2–11. MCLK PLL Registers
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
N value
1
1
N5
N4
N3
N2
N1
N0
M value
0
0
M5
M4
M3
M2
M1
M0
P value
PLLEN
0
1
1
0
0
P1
P0
Status
X
LOCK
X
X
X
X
X
X
Table 2–12. MCLK/Loop Clock Control Register (Index: 0x39, Access: R/W, Default: 0x18)
BIT NAME
VALUES
DESCRIPTION
MKC7, MKC6,
00
Reserved
MKC5
0: Pixel clock PLL
(default)
1:Loop clock PLL
Selects signal to output on RCLK terminal. Pixel clock PLL is selected as
default to support VGA mode 2. In VGA mode 2, the graphics accelerator
receives RCLK and returns its VGA output clock to the CLK0 terminal
along with synchronous VGA data. Select loop clock PLL for all modes
using LCLK data latching. These include all modes using the pixel port
P127–P0 and VGA mode 1 which uses LCLK latching of VGA7–VGA0.
MKC4
0: Dot clock
1: MCLK PLL (default)
Selects signal to output on MCLK terminal. MCLK PLL is selected as
default. Select dot clock to ensure a stable output on MCLK while MCLK
PLL frequency is reprogrammed. See Section 2.5.2.1. A change of this
bit does not take effect until a logic 0 to logic 1 transition of bit MKC3
occurs, during which bit MKC4 should not be changed.
MKC3
0:
1: (default)
Strobe for MCLK terminal output multiplexer control (MKC4). A logic 0 to
logic 1 transition of this bit strobes in bit MKC4, causing bit MKC4 to take
effect. While the logic 0 to logic 1 transition occurs on MKC3, MKC4
should not be changed.
MKC2, MKC1,
MKC0
000: Divide by 2 (default)
001: Divide by 4
010: Divide by 6
011: Divide by 8
100: Divide by 10
101: Divide by 12
110: Divide by 14
111: Divide by 16
Loop clock PLL post scalar Q divider. This additional frequency division
is applied after the 2P division of the loop clock PLL P-value register. For
a binary value of Q in MKC2–MKC0, the resulting frequency division is
2*(Q+1).
After device reset, the MCLK PLL outputs a 50.11 MHz clock frequency and the pixel clock PLL output
depends on the PLLSEL1 and PLLSEL0 inputs according to Table 2–10. These frequencies assume a
standard 14.31818 MHz crystal reference.
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