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參數(shù)資料
| 型號： | TVP3030-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 13/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-175 |
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1–7
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
91, 92
HSYNCOUT,
VSYNCOUT
O
Horizontal and vertical sync outputs. These outputs are pipeline delayed
versions of the selected sync inputs. Output polarity inversion may be
independently selected using general control register bits GCR(1,0).
Analog current outputs. These outputs can drive a 37.5-
load directly (doubly
terminated 75-
line), thus eliminating the requirement for any external buffering.
IOR, IOG,
IOB
94, 96, 98
O
LCLK
159
I
Latch clock input. LCLK is used to latch pixel-bus-input data and system video
controls. VGA data may also be latched with LCLK if so selected. LCLK may be
a delayed version of RCLK or a divided and delayed version of RCLK provided
that linear phase changes in RCLK cause corresponding linear phase changes
in LCLK.
MCLK
157
O
Memory clock output. MCLK is the output of an independently programmable
PLL frequency synthesizer. The dot clock may be output on this terminal while
the MCLK frequency is reprogrammed.
PCLKOUT
177
O
Pixel clock PLL output. PCLKOUT is a buffered version of the pixel clock PLL
output and is mainly for test purposes. This output is independent of the dot clock
source selected by the clock selection register.
PLLGND
175
Ground for regulated PLL supplies. Decoupling capacitors should be connected
between PLLVDD and PLLGND. PLLGND should be connected to the system
ground plane through a ferrite bead.
PLLVDD
176, 178
PLL power supply. PLLVDD must be a well regulated 5 V power supply voltage.
Decoupling capacitors should be connected between PLLVDD and PLLGND.
Terminal 176 supplies power to the pixel clock PLL. Terminal 178 supplies power
to the MCLK PLL and the loop clock PLL.
OVS
120
I
Overscan input. OVS is used to control the display of custom screen borders. If
OVS is not used, it should be connected to GND.
ODD/EVEN
158
I
Odd or even field display. ODD/EVEN indicates odd or even field during
interlaced display for cursor operation. Logic 0 indicates the even field and logic
1 indicates the odd field.
PLLSEL1,
PLLSEL0
179, 180
I
Pixel clock PLL frequency selection. Selects among two fixed frequencies and
the programmed frequency of the pixel clock PLL.
P127–P0
1–26,
31–63,
80–84,
87, 88,
129–152,
162–171,
181–208
I
Pixel input port. The port can be used in various multiplexing modes. Unused
terminals should not be allowed to float.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-175PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-175PPM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
| TVP3030-230PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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