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參數(shù)資料
| 型號(hào)： | TSC2008TRGVRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, PLASTIC, VQFN-16 |
| 文件頁數(shù)： | 18/35頁 |
| 文件大小： | 418K |
| 代理商： | TSC2008TRGVRQ1 |
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t
ACQ
Idle
Acquire
Conv
1
0
Idle
1
SCLK
CS
8
1
11
SDO
Drivers1and2
(1)
(SER/DFRHigh)
Drivers1and2
(1, 2)
(SER/DFRLow)
(MSB)
(START)
(LSB)
A2
S
On
Off
SDI
A1
A0 MODE
SER/
DFR
PD1 PD0
10
9
8
7
6
5
4
3
2
1
0
ZeroFilled...
8
1
8
NOTES: (1)ForY-Position,Driver1isonX+isselected,andDriver2isoff.ForX-Position,Driver1isoff,Y+isselected,andDriver2ison.Y willturnon
-
whenpower-downmodeisenteredandPD0=0.
(2)DriverswillremainonifPD0=1(nopowerdown)untilselectedinputchannel,orpower
ishigh.
-downmodeischanged,or CS
PENIRQ
HIGH: Disableor(EnableandNotTouched)
New
Definition
PENIRQ
LOW: EnableandTouched
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
1
SCLK
CS
8
1
SDO
PENIRQ
S
SDI
ControlBits
S
ControlBits
HIGH: Disableor(EnableandNotTouched)
NewPENIRQDefinition
LOW: EnableandTouched
8
1
8
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
A2
1
A1 A0 MODE
SER/
DFR
PD1 PD0
A2 A1 A0 MODE
SER/
DFR
PD1 PD0
n
n +1
n
n +1
HIGH: Disableor
(EnableandNotTouched)
LOW: EnableandTouched
Idle
Acquire Conv
Idle
Acquire Conv
Idle
SBAS552
– JUNE 2011
12-BIT OPERATION TIMING
A single touch result can be easily achieved using 24 SCLKs per cycle operation when the 12-bit ADC mode is
used, as shown in Figure 31. However, because this operation uses slightly more bus bandwidth, a more efficient
method is to overlap the control bytes with the conversion result using 16 SCLKs per cycle operation; see
Figure 31. Conversion Timing
—12-Bit Mode, 24 SCLKs per Cycle, 8-Bit Bus Interface
The control bits for conversion n + 1 can be overlapped with conversion n to allow for a conversion every 16
clock cycles, as shown in Figure 32. After submitting the control bits, the TSC2008-Q1 uses the internal clock to
acquire data from seven conversions (see Figure 29). Deselecting the TSC2008-Q1 (CS = '1') during this time
period allows the host to communicate with the other peripherals using the same SPI bus before reading out the
ADC data.
Figure 32. Conversion Timing
—12-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, with Earliest Start
of New Command
Copyright
2011, Texas Instruments Incorporated
25
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