參數(shù)資料
型號： TSC2008TRGVRQ1
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC16
封裝： 4 X 4 MM, PLASTIC, VQFN-16
文件頁數(shù)： 16/35頁
文件大?。?/td> 418K
代理商： TSC2008TRGVRQ1
SBAS552
– JUNE 2011
PD0 and PD1
—The power-down bits select the power-down mode that the TSC2008-Q1 will be in after the
current command completes, as shown in Table 5.
It is recommended to set PD0 = '0' in each command byte to get the lowest power consumption possible. If
multiple X-, Y-, and Z-position measurements are performed sequentially (such as when averaging),
PD0 = '1' leaves the touch screen drivers on at the end of each conversion cycle.
Table 5. Power-Down and Internal Reference Selection
PD1
PD0
PENIRQ
DESCRIPTION
Power-Down Between Conversions. When each conversion is finished, the
converter enters a low-power mode. At the start of the next conversion, the
0
Enabled
device instantly powers up to full power. There is no need for additional delays to
ensure full operation, and the very first conversion is valid. The Y
– switch is on
when in power-down.
0
1
Disabled
A/D converter on. PENIRQ disabled.
1
0
Enabled
A/D converter off. PENIRQ enabled.
1
Disabled
A/D converter on. PENIRQ disabled.
Variable Resolution
The TSC2008-Q1 provides either 8-bit or 12-bit resolution for the A/D converter. Lower resolution is often
practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower
resolution reduces the amount of time it takes for the A/D converter to complete its conversion process, which
also lowers power consumption.
8- and 12-Bit Conversion
The TSC2008-Q1 provides both 12-bit or 8-bit conversion modes.
The 12-bit conversion mode can be done in 24 SCLKs per cycle or 16 SCLKs per cycle timing; see Figure 31
and Figure 32 for details. The 8-bit conversion can be done in 24 SCLKs per cycle (although this mode is
unlikely to be selected), 16 SCLKs per cycle, or even 8 SCLKs per cycle (when adjusted SDO timing is selected);
see Figure 33 and Figure 34 for details.
The 8-bit mode can be used when faster throughput is needed and the digital result is not as critical. By
switching to the 8-bit conversion mode, a conversion is complete four internal conversion clock cycles earlier and
also takes less time to transfer the result. The internal conversion clock runs at twice the speed (4MHz typical)
than the 12-bit conversion mode. This faster conversion and transfer saves power.
Conversion Clock and Conversion Time
The TSC2008-Q1 contains an internal clock that drives the state machines that perform the many functions of
the device. This clock is divided down to provide a clock that runs the A/D converter. The 8-bit ADC mode uses a
4MHz clock and the 12-bit ADC mode uses a 2MHz clock. The actual frequency of this internal clock is slower
than the name suggests, and varies with the supply voltage.
Copyright
2011, Texas Instruments Incorporated
23
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