參數(shù)資料
型號(hào): TS83102G0BVGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁數(shù): 4/60頁
文件大?。?/td> 1510K
代理商: TS83102G0BVGL
12
0830E–BDC–06/07
TS83102G0B
e2v semiconductors SAS 2007
Note:
1. Unless otherwise specified
Only minimum and maximum values are guaranteed (typical values are issued from characterization results).
Figure 7-1.
Timing Diagram
Note:
Detailed timing diagrams are provided on page 38
Table 7-1.
Explanation of Test Levels
Level
Explanation
1
100% production tested at 25°C (1) (for "C" temperature range) (2)
2
100% production tested at 25°C (1) and sample tested at specified temperatures (for "V" temperature ranges (2))
3
Sample tested only at specified temperatures
4
Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified
temperature)
5
Parameter is a typical value guaranteed by design only
6
100% production tested over specified temperature range (for "B/Q" temperature range (2))
Pipeline Delay = 4 clock cycles
TOD
TD1 TD2
TDR
Gray to Binary decoding
Logic encoding
NN+1
N+2
NN+1
N+2
NN+1
N+2
NN+1
N+2
NN+1
N+2
NN+1
N+2
NN+1
N+2
NN+1
N+2
Latch 1
Latch 2
Latch 3
Latch 4
Latch 5
Latch 6
Latch 7
Latch 8
Data ready
Outputs
Internal clock
External clock
Analog input
Output
Latches
Regeneration
Latches
TA
N
N+1
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