參數(shù)資料
型號: TS83102G0BVGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA152
封裝: 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-152
文件頁數(shù): 16/60頁
文件大?。?/td> 1510K
代理商: TS83102G0BVGL
23
0830E–BDC–06/07
e2v semiconductors SAS 2007
TS83102G0B
Figure 10-11. SFDR Versus Input
Frequency at Fs = 1.4 Gsps
and Fs = 1.7 Gsps
Figure 10-12. SNR Versus Input
Frequency at Fs = 1.4 Gsps
and Fs = 1.7 Gsps
10.1.6
Typical Reconstructed Signals and Signal Spectrum
The ADC input signal is sampled at a full sampling rate, but the output data is 8 or 16 times decimated so
as to relax the acquisition system data rate. As a consequence, the calculation software sees an effec-
tive frequency divided by 8 or 16, compared to the ADC clock frequency used (Fs). The spectrum is thus
displayed from DC to Fs/2 divided by the decimation factor.
Decimation only folds all spectral components between DC and Fs/2 divided by the decimation factor but
does not change their amplitude.
This does not have any impact on the FFT spectral characteristics because of the ergodicity of the sam-
ples (time average = statistic average). The input frequency is chosen to respect the coherence of the
acquisition.
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Fin (MHz)
SFDR
(dBc)
Fs = 1.4 Gsps
Fs = 1.7 Gsps
30
35
40
45
50
55
60
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Fin (MHz)
SNR
(dB)
Fs = 1.4 Gsps
Fs = 1.7 Gsps
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