參數(shù)資料
型號(hào)： TS68C000DESC01ZCA
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 8 MHz, MICROPROCESSOR, CQFP68
封裝： GOLD PLATED, CERAMIC, QFP-68
文件頁(yè)數(shù)： 41/52頁(yè)
文件大小： 667K
代理商： TS68C000DESC01ZCA
46
2170A–HIREL–09/05
TC68C000
Notes:
1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maxi-
mum columns.
2. If the asynchronous setup time (47) requirements are satisfied, the DTACK low-to-data setup time (31) required can be
ignored. The data must only satisfy the date in clock-low setup time (27) for the following cycle.
3. The falling edge of S6 triggers both the negation of the strobes (AS and X DS) and the falling edge of E. Either of these
events can occur first, depending upon the loading on each signal specification 49 indicates the absolute maximum skew
that will occur between the rising edge of the strobes and the falling edge of the E clock.
Figure 2-17. TS68C000 to EF6800 Peripheral Timing Diagram – Best Case
Note:
This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly
attainable.
45
ELCAI
E low to control, address bus invalid
(address hold time)
30
10
ns
47
ASI
Asynchronous input setup time(2)
20
ns
49
SHEL
AS, DS high to E low(3)
-7070-55
55
-80
ns
50
EH
E width high
450
350
280
ns
51
EL
E width low
700
550
440
ns
54
ELDOI
E low to data out invalid
30
20
15
ns
Table 2-13.
Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral (Continued)
Number
Symbol
Parameter
8 MHz
10 MHz
12.5 MHz
Unit
Limits
Min
Max
Min
Max
Min
Max
S0
S1
S2
S3
S4
A1-A23
CLK
AS
R/W
E
VPA
VMA
DATA OUT
DATA IN
23
18
41
20
42
51
41
40
43
50
42
41
12
49
18
44
45
41
54
29
27
45
S5
S6
S7 S0
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