- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄199476 > TS68C000DESC01ZCA (E2V TECHNOLOGIES PLC) 32-BIT, 8 MHz, MICROPROCESSOR, CQFP68 PDF資料下載
參數(shù)資料
| 型號(hào)： | TS68C000DESC01ZCA |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 8 MHz, MICROPROCESSOR, CQFP68 |
| 封裝： | GOLD PLATED, CERAMIC, QFP-68 |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 667K |
| 代理商： | TS68C000DESC01ZCA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
41
2170A–HIREL–09/05
TS68C000
2.7.5
Processing States
The TS68C000 is always in one of three processing states: normal, exception, or halted.
2.7.5.1
Normal Processing
The normal processing state is that associated with instruction execution; the memory refer-
ences are to fetch instructions and operands, and to store results. A special case of normal state
is the stopped state which the processor enters when a stop instruction is executed. In this state,
no further references are made.
2.7.5.2
Exception Processing
The exception processing state is associated with interrupts, trap instructions, tracing, and other
exception conditions. The exception may be internally generated by an instruction or by an
unusual condition arising during the execution of an instruction. Externally, exception processing
can be forced by an interrupt, by a bus error, or by a reset. Exception processing is designed to
provide an efficient context switch so that the processor may handle unusual conditions.
2.7.5.3
Halted Processing
The halted processing state is an Indication of catastrophic hardware failure. For example, if dur-
ing the exception processing of a bus error another bus errors occurs, the processor assumes
that the system is unusable and halts. Only an external reset can restart a halted processor.
Note that a processor in the stopped state is not in the halted state, nor vice versa.
Asserting the reset and halt line for ten cycles will cause a processor reset, except when VCC is
initially applied to the processor. In this case, an external reset must be applied for least 100
milliseconds.
2.7.6
Interface with EF 6800 Peripherals
Extensive line of EF6800 peripherals are directly compatible with the TS68C000.
Note: It is the own user's responsibility to verify the actual EF 6800 peripheral performances to
be compatible to the actual used TS68C000 microprocessor performances.
Soma of the EF 6800 peripheral that are particularly useful are:
EF6821: Peripheral lnterface Adapter
EF6840: Programmable Timer Module
EF6850: Asynchronous Communications Interface Adapter
EF6852: Synchronous Serial Data Adapter
EF6854: Advanced Data Link Controller
To interface the synchronous EF 6800 peripherals with the asynchronous TS68C000, the pro-
cessor modifies its bus cycle to meet the EF 6800 cycle requirements whenever an EF 6800
device address is detected. This is possible since both processors use memory mapped 1/0.
Figure 2-13 is a flowchart of the interface operation between the processor and EF 6800
devices.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TS68C000DESC02ZCA | 32-BIT, 10 MHz, MICROPROCESSOR, CQFP68 |
| TS7905CZC0 | 5 V FIXED NEGATIVE REGULATOR, SFM3 |
| TS7905CZC0G | 5 V FIXED NEGATIVE REGULATOR, SFM3 |
| TS7905CIC0 | 5 V FIXED NEGATIVE REGULATOR, SFM3 |
| TS79L09CYRM | 9 V FIXED NEGATIVE REGULATOR, PSSO3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS68C000DESC02UAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC02UCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC02XAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC02XCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
| TS68C000DESC02YAA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER HCMOS 16/32 BIT MICROPROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。