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參數(shù)資料
| 型號(hào)： | TPS62410DRCTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.6 A DUAL SWITCHING CONTROLLER, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | 3 X 3 MM, GREEN, PLASTIC, MLF-10 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 1240K |
| 代理商： | TPS62410DRCTG4 |
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100% Duty Cycle Low Dropout Operation
Vin
min + Voutmax ) Ioutmax
RDSonmax ) RL
(3)
Under-Voltage Lockout
MODE SELECTION
ENABLE
SLVS737 – FEBRUARY 2007
DETAILED DESCRIPTION (continued)
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range; i.e., the minimum input voltage to maintain regulation depends on the load current and output
voltage, and can be calculated as:
With:
Iout
max = maximum output current plus inductor ripple current
RDSon
max = maximum P-channel switch RDSon
R
L = DC resistance of the inductor
Vout
max = nominal output voltage plus maximum output voltage tolerance
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the converters. The under-voltage lockout threshold is typically
1.5V, max 2.35V. In case the default register values are overwritten by the Interface, the new values in the
registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the
under-voltage lockout threshold, independent of whether the converters are disabled.
The MODE/DATA pin allows mode selection between forced PWM Mode and Power Save Mode for both
converters. Furthermore, this pin is a multipurpose pin and provides (besides Mode selection) a one-pin
interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale
Interface.
Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters
operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light
load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power
save mode during light loads. For additional flexibility it is possible to switch from Power Save Mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the
converter to the specific system requirements.
In case the operation mode will be changed from forced PWM mode (MODE/DATA = high) to Power Save Mode
Enable (MODE/DATA = 0) the Power Save Mode will be enabled after a delay time of typically ttimeout, which is a
maximum of 520
s.
The forced PWM Mode operation is enabled immediately with Pin MODE/DATA set to 1.
The device has for each converter a separate EN pin to start up each converter independently. If EN1, EN2 are
set to high, the corresponding converter starts up with soft start as previously described.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically
1.2
A. In this mode, the P and N-Channel MOSFETs are turned-off and the entire internal control circuitry is
switched-off. For proper operation the EN1 and EN2 pins must be terminated and must not be left floating.
16
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