參數(shù)資料
型號: TPS61170DRV
廠商: Texas Instruments, Inc.
英文描述: 1.2A High Voltage Boost Converter in 2x2mm2 QFN Package
中文描述: 1.2A的高電壓升壓轉(zhuǎn)換器2x2mm2 QFN封裝
文件頁數(shù): 9/22頁
文件大?。?/td> 405K
代理商: TPS61170DRV
www.ti.com
FEEDBACK REFERENCE PROGRAM MODE SELECTION
The CTRL pin is used for changing the FB pin reference voltage
on-the-fly
. There are two methods to program
the reference voltage, PWM signal and 1 wire interface (EasyScale). The program mode is selected each time
the device is enabled. The default mode is the PWM signal which uses the duty cycle of the CTRL pin signal to
modulate the reference voltage. To enter the 1 wire interface mode, the following digital pattern on the CTRL pin
must be recognized by the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61170 and to start the 1 wire mode detection window.
2. After the EasyScale detection delay (t
es_delay
, 100
μ
sec) expires, drive CTRL low for more than the EasyScale
detection time (t
es_detect
, 260
μ
sec).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window
(t
es_win
, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1 wire mode once the above 3 conditions are met. The EasyScale communication
can start before the detection window expires. Once the mode is programmed, it can not be changed without
another start up. This means the IC needs to be shutdown by pulling the CTRL low for 2.5ms and restarts. See
the
Mode Detection of Feedback Reference Program
figure (
Figure 13
) for a graphical explanation.
CTRL
low
high
FB
200mV x duty cycle
Insert battery
CTRL
low
high
FB
Insert battery
Programming
code
FB ramp
Shutdown delay
t
Enter ES mode
Timing window
Programming code
50mV
50mV
Enter ES mode
PWM signal
Startup
delay
PWM
mode
Startup delay
FB ramp
Programmed value
(if not programmed 200mV default)
Shutdown
delay
IC
Shutdown
Startup delay
FB ramp
ES
mode
ES detect delay
ES detect time
PWM PROGRAM MODE
When the CTRL pin is constantly high, the FB voltage is regulated to 1.229V typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage. The relationship between the duty cycle and FB voltage is
given in
Equation 1
:
V
FB
Duty
1.229 V
(1)
TPS61170
SLVS789–NOVEMBER 2007
Figure 13. Mode Detection of Feedback Reference Program
Where:
Duty = duty cycle of the PWM signal
1.229 V = internal reference voltage
As shown in
Figure 14
, the IC chops up the internal 1.229V reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. The regulation voltage is independent of the
PWM logic voltage level which often has large variations.
For optimum performance, use the PWM mode in the range of 5kHz to 100kHz. The requirement of minimum
frequency comes from the EasyScale detection delay and detection time specification for the mode selection.
The device can mistakenly enter 1 wire mode if the PWM signal frequency is less than 5kHz. Since the CTRL pin
is logic only pin, adding external RC filter to the pin does not work.
Copyright 2007, Texas Instruments Incorporated
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