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參數(shù)資料
| 型號(hào)： | TP28F010-120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 120 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁(yè)數(shù)： | 15/33頁(yè) |
| 文件大?。?/td> | 895K |
| 代理商： | TP28F010-120 |
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E
28F010
15
Start Erasure
(4)
Data = 00H
Program All
Bytes to 00H
Apply V
PPH
(1)
ADDR = 00H
PLSCNT = 0
Time Out 10 ms
Time Out 6 μs
Read Data
from Device
Data = FFH
Inc
PLSCNT =
1000
Last Address
Erasure
Completed
Erase Error
Write Erase
Set-Up Cmd
Write Erase Cmd
Write Read Cmd
Apply V
PPL
(1)
Apply V
PPL
(1)
Write Erase
Verify Cmd
Increment Addr
Y
Bus
Operation
Comments
Entire Memory Must = 00H
Before Erasure
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Standby
Wait for V
PP
Ramp to V
PPH
(1)
Initialize Addresses and
Pulse-Count
Write
Data = 20H
Write
Data = 20H
Stand-by
Duration of Erase Operation
(t
WHWH2
)
Write
Addr = Byte to Verify;
Data = A0H; Stops Erase
Operation
(3)
Standby
t
WHGL
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Standby
Wait for V
PP
Ramp to V
PPL
(1)
N
Y
N
N
N
Y
Y
Command
Set-Up
Erase
Erase
Erase
(2)
Verify
Write
Data = 00H, Resets the
Register for Read Operations
Read
0207_05
NOTES:
1.
2.
See DC Characteristicsfor the value of V
PPH
and V
PPL
.
Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is
written with the Read command.
Refer to Principles of Operation
CAUTION:
The algorithm
must be followed
to ensure proper and reliable operation of the device.
3.
4.
Figure 5. 28F010 Quick-Erase Algorithm
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