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參數(shù)資料
| 型號： | TN80L188EB13 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| 中文描述： | 16-BIT, 13 MHz, MICROPROCESSOR, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 8/59頁 |
| 文件大?。?/td> | 779K |
| 代理商： | TN80L188EB13 |
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80C186EB/80C188EB, 80L186EB/80L188EB
PACKAGE INFORMATION
This section describes the pins, pinouts, and thermal
characteristics for the 80C186EB in the Plastic
Leaded Chip Carrier (PLCC) package, Shrink Quad
Flat Pack (SQFP), and Quad Flat Pack (QFP) pack-
age. For complete package specifications and infor-
mation, see the Intel Packaging Outlines and Dimen-
sions Guide (Order Number: 231369).
Prefix Identification
With the extended temperature range, operational
characteristics are guaranteed over the temperature
range corresponding to
b
40
§
C to
a
85
§
C ambient.
Package types are identified by a two-letter prefix to
the part number. The prefixes are listed in Table 1.
Table 1. Prefix Identification
Prefix Note
Package
Type
Temperature
Type
TN
PLCC
Extended
TS
QFP (EIAJ) Extended
SB
1
SQFP
Extended/Commercial
N
1
PLCC
Commercial
S
1
QFP (EIAJ) Commercial
NOTE:
1. The 5V 25 MHz and 3V 16 MHz versions are only avail-
able in commercial temperature range corresponding to
0
§
C to
a
70
§
C ambient.
Pin Descriptions
Each pin or logical set of pins is described in Table
3. There are three columns for each entry in the Pin
Description Table.
The
Pin Name
column contains a mnemonic that
describes the pin function. Negation of the signal
name (for example, RESIN) denotes a signal that is
active low.
The
Pin Type
column contains two kinds of informa-
tion. The first symbol indicates whether a pin is pow-
er (P), ground (G), input only (I), output only (O) or
input/output (I/O). Some pins have multiplexed
functions (for example, A19/S6). Additional symbols
indicate additional characteristics for each pin. Table
2 lists all the possible symbols for this column.
The
Input Type
column indicates the type of input
(Asynchronous or Synchronous).
Asynchronous pins require that setup and hold times
be met only in order to guarantee recognition at a
particular clock edge. Synchronous pins require that
setup and hold times be met to guarantee proper
operation. For example, missing the setup or hold
time for the SRDY pin (a synchronous input) will re-
sult in a system failure or lockup. Input pins may also
be edge- or level-sensitive. The possible character-
istics for input pins are S(E), S(L), A(E) and A(L).
The
Output States
column indicates the output
state as a function of the device operating mode.
Output states are dependent upon the current activi-
ty of the processor. There are four operational
states that are different from regular operation: bus
hold, reset, Idle Mode and Powerdown Mode. Ap-
propriate characteristics for these states are also in-
dicated in this column, with the legend for all possi-
ble characteristics in Table 2.
The
Pin Description
column contains a text de-
scription of each pin.
As an example, consider AD15:0. I/O signifies the
pins are bidirectional. S(L) signifies that the input
function is synchronous and level-sensitive. H(Z)
signifies that, as outputs, the pins are high-imped-
ance upon acknowledgement of bus hold. R(Z) sig-
nifies that the pins float during reset. P(X) signifies
that the pins retain their states during Powerdown
Mode.
8
8
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