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參數(shù)資料
| 型號： | TN28F020-120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| 中文描述： | 256K X 8 FLASH 12V PROM, 120 ns, PQCC32 |
| 封裝： | 0.450 X 0.550 INCH, PLASTIC, LCC-32 |
| 文件頁數(shù)： | 12/38頁 |
| 文件大?。?/td> | 878K |
| 代理商： | TN28F020-120 |
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28F020
E
12
The 28F020 contains an intelligent identifier
operation
to
supplement
programming methodology. The operation is
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of BDH. To terminate the operation, it
is necessary to write another valid command into
the register.
traditional
PROM-
2.2.2.3
Set-Up Erase/Erase Commands
Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.
To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).
This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the V
PP
pin.
In the absence of this high voltage, memory
contents are protected against erasure. Refer to
AC
Characteristics
—Write/Erase/Program
Operations
and waveforms for specific timing
parameters.
Only
2.2.2.4
Erase Verify Command
The Erase command erases all bytes of the array
in parallel. After each erase operation, all bytes
must be verified. The erase verify operation is
initiated by writing A0H into the command register.
The address for the byte to be verified must be
supplied as it is latched on the falling edge of the
WE# pulse. The register write terminates the erase
operation with the rising edge of its WE# pulse.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The Erase Verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH,
another erase operation is performed. (Refer to
Section 2.2.2.3,
Set-Up Erase/Erase Commands
.)
Verification then resumes from the address of the
last verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this point, the verify
operation is terminated by writing a valid command
(e.g., Program Set-Up) to the command register.
Figure 5, the
28F020 Quick-Erase Algorithm
flowchart, illustrates how commands and bus
operations are combined to perform electrical
erasure
of
the
28F020.
Characteristics—Write/Erase/Program Only Oper-
ations
and
waveforms
parameters.
Refer
to
AC
for
specific
timing
2.2.2.5
Set-Up Program/Program
Commands
Set-Up program is a command-only operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WE# pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the rising edge of the WE#
pulse. The rising edge of WE# also begins the
programming
operation.
operation terminates with the next rising edge of
WE# used to write the Program Verify command.
Refer to
AC Characteristics—Write/Erase/Program
Only Operations
and waveforms for specific timing
parameters.
The
programming
2.2.2.6
Program Verify Command
The 28F020 is programmed on a byte-by-byte
basis. Byte programming may occur sequentially or
at random. Following each programming operation,
the byte just programmed must be verified.
The program verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TN28F020-150 | 制造商:Intel 功能描述:NOR Flash, 256K x 8, 32 Pin, Plastic, PLCC |
| TN28F020-90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F020 2048K (256K X 8) CMOS FLASH MEMORY |
| TN28F512-120 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intel 功能描述: |
| TN29/19/15-3E25 | 制造商:FERROXCUBE 功能描述:FERRITE CORE TOROID 3E25 制造商:FERROXCUBE 功能描述:FERRITE TN29/19/15-3E25 制造商:Yageo / Ferroxcube 功能描述:FERRITE CORE, TOROID, 3E25 制造商:FERROXCUBE 功能描述:FERRITE CORE, TOROID, 3E25; Core Type:Toroid; Core Size:TN29; Material Grade:3E25; Effective Magnetic Path Length:73.2mm; Ae Effective Cross Section Area:73.9mm2; Inductance Factor Al:7000nH; SVHC:No SVHC (18-Jun-2012); External ;RoHS Compliant: Yes |
| TN29/19/7.5 | 制造商:FERROXCUBE 制造商全稱:Ferroxcube International Holding B.V. 功能描述:Ferrite toroids |
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