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參數(shù)資料
| 型號： | TMX320F28044ZGMQ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 57/107頁 |
| 文件大?。?/td> | 784K |
| 代理商： | TMX320F28044ZGMQ |
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4.7
Serial Peripheral Interface (SPI) Module (SPI-A)
Baud rate =
LSPCLK
4
LSPCLK
(SPIBRR
1)
when SPIBRR = 3 to 127
Baud rate =
when SPIBRR = 0,1, 2
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
The F28044 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
Four external pins:
–
SPISOMI: SPI slave-output/master-input pin
–
SPISIMO: SPI slave-input/master-output pin
–
SPISTE: SPI slave transmit-enable pin
–
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
–
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
–
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
–
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
16-level transmit/receive FIFO
Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in
Table 4-8
.
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Peripherals
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320F28044ZGMS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processor |
| TMX320F28045GGMA | 制造商:Texas Instruments 功能描述:TMS320F28044, TMS320F28045 DIGITAL CONTROLLERS - Trays |
| TMX320F28045PZA | 制造商:Texas Instruments 功能描述:TMS320F28044, TMS320F28045 DIGITAL CONTROLLERS - Trays |
| TMX320F28045ZGMA | 制造商:Texas Instruments 功能描述:TMS320F28044, TMS320F28045 DIGITAL CONTROLLERS - Trays |
| TMX320F28055PNT | 功能描述:32位微控制器 - MCU GIZMO MASS MARKET RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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