參數(shù)資料
型號: TMX320F28044ZGMQ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號處理器
文件頁數(shù): 103/107頁
文件大小: 784K
代理商: TMX320F28044ZGMQ
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6.13 Flash Timing
t
a(fp)
t
c(SCO)
1 (round up to the next highest integer) or 0, whichever is larger
t
a(fr)
t
c(SCO)
1
(round up to the next highest integer) or 1, whichever is larger
Flash Page Wait-State
Flash Random Wait-State
(round up to the next highest integer) or 1, whichever is larger
t
a(OTP)
t
c(SCO)
1
OTP Wait-State
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Table 6-35. Flash Endurance
MIN
100
TYP
1000
MAX
UNIT
cycles
write
N
f
N
OTP
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
0
°
C to 85
°
C (ambient)
0
°
C to 85
°
C (ambient)
1
Table 6-36. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
50
500
10
75
35
140
MAX
UNIT
μ
s
ms
S
mA
mA
mA
Program
Time
16-Bit Word
16K Sector
16K Sector
V
current consumption during the
Erase/Program cycle
Erase Time
I
DD3VFLP
Erase
Program
I
DDP
V
current consumption during Erase/Program
cycle
V
current consumption during Erase/Program
cycle
I
DDIOP
20
mA
(1)
Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.
Table 6-37. Flash/OTP Access Timing
PARAMETER
MIN
36
36
60
TYP
MAX
UNIT
ns
ns
ns
t
a(fp)
t
a(fr)
t
a(OTP)
Paged flash access time
Random flash access time
OTP access time
Equations to compute the Flash page wait-state and random wait-state in
Table 6-38
are as follows:
Equation to compute the OTP wait-state in
Table 6-38
is as follows:
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Electrical Specifications
103
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