參數(shù)資料
型號： TMX320C6415TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 43/140頁
文件大小： 2033K
代理商： TMX320C6415TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
I
Device reset
NMI
B4
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it
is recommended that the NMI pin be grounded versus relying on the IPD.
GP7/EXT_INT7
AF4
default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
General-purpose input/output (GPIO) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at default.
GPIO 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GPIO 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GPIO 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GPIO 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GPIO 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GPIO 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
GPIO 3 pin (
I/O/Z
). The default after reset setting is GPIO 3 enabled as input-only.
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (
I/O/Z
) can be programmed as GPIO 0 (
input only
)
[default] or as GPIO 0 (
output only
) pin or output as a general-purpose interrupt (GP0INT)
signal (
output only
).
McBSP2 external clock source (CLKS2) [
input only
] [default] or this pin can be pro-
grammed as a GPIO 8 pin (
I/O/Z
).
GP6/EXT_INT6
AD5
I/O/Z
IPU
General-purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
). The
GP5/EXT_INT5
AE5
GP4/EXT_INT4
GP15/PRST§
GP14/PCLK§
GP13/PINTA§
GP12/PGNT§
GP11/PREQ§
GP10/PCBE3§
GP9/PIDSEL§
AF5
G3
F2
G4
J3
F1
L2
I/O/Z
M3
GP3
AC6
IPD
GP0
AF6
IPD
CLKS2/GP8§
AE4
I/O/Z
IPD
CLKOUT6/GP2§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 2 pin (
I/O/Z
).
CLKOUT4/GP1§
AE6
I/O/Z
IPD
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 1 pin (
I/O/Z
).
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415T or C6416T devices only]
PCI_EN
AA4
I
IPD
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals. This pin works in conjunction with the MCBSP2_EN pin to enable/disable
other peripherals (for more details, see the Device Configurations section of this data sheet).
HINT/PFRAME§
R4
I/O/Z
Host interrupt from DSP to host (
O
) [default] or PCI frame (
I/O/Z
)
HCNTL1/
PDEVSEL§
R1
I/O/Z
Host control selects between control, address, or data registers (
I
) [default] or PCI device
select (
I/O/Z
).
HCNTL0/
PSTOP§
T4
I/O/Z
Host control selects between control, address, or data registers (
I
) [default] or PCI stop
(
I/O/Z
)
HHWIL/PTRDY§
R3
I/O/Z
Host half-word select first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (
I
) [default] or PCI target ready (
I/O/Z
)
HR/W/PCBE2§
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§For the C6415T and C6416T devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414T device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
For the C6414T device, only these pins are multiplexed pins.
P1
I/O/Z
Host read or write select (
I
) [default] or PCI command/byte enable 2 (
I/O/Z
)
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