參數(shù)資料
型號： TMX320C6415TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 21/140頁
文件大?。?/td> 2033K
代理商： TMX320C6415TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
peripheral register descriptions (continued)
Table 10. Interrupt Selector Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU
interrupts 1015 (INT10INT15)
Selects which interrupts drive CPU
interrupts 49 (INT04INT09)
Sets the polarity of the external
interrupts (EXT_INT4EXT_INT7)
019C 0004
MUXL
Interrupt multiplexer low
019C 0008
EXTPOL
External interrupt polarity
019C 000C 019C 01FF
Reserved
Table 11. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
The CPU and EDMA controller
can only read this register;
they cannot write to it.
0x3000 0000 0x33FF FFFF
018C 0004
0x3000 0000 0x33FF FFFF
018C 0008
018C 000C
018C 0010
018C 0014
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 018F FFFF
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCERE00
XCERE00
PCR0
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
McBSP0 receive control register
McBSP0 transmit control register
McBSP0 sample rate generator register
McBSP0 multichannel control register
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
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