參數(shù)資料
型號： TMX320C6414TGLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 83/140頁
文件大?。?/td> 2033K
代理商： TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
83
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN for EMIFA and EMIFB
§
(see Figure 19)
NO.
600
720
850
1G
UNIT
MIN
6#
7.5#
MAX
16P
1
tc(EKI)
Cycle time, ECLKIN
CVDD = 1.2 V
CVDD = 1.1 V
ns
16P
ns
2
tw(EKIH)
tw(EKIL)
tt(EKI)
tJ(EKI)
Pulse duration, ECLKIN high
2.7
ns
3
Pulse duration, ECLKIN low
2.7
ns
4
Transition time, ECLKIN
2
ns
5
Period jitter, ECLKIN
0.02E
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
#Minimum ECLKIN cycle times
must
be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the devices, 133-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met.
ECLKIN
2
3
4
4
5
1
Figure 19. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and
EMIFB modules
§||
(see Figure 20)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
±
175
EH + 0.7
1
tJ(EKO1)
tw(EKO1H)
tw(EKO1L)
tt(EKO1)
td(EKIH-EKO1H)
td(EKIL-EKO1L)
§These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
||The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
Period jitter, ECLKOUT1
0
ps
2
Pulse duration, ECLKOUT1 high
EH 0.7
ns
3
Pulse duration, ECLKOUT1 low
EL 0.7
EL + 0.7
ns
4
Transition time, ECLKOUT1
1
ns
5
Delay time, ECLKIN high to ECLKOUT1 high
0.8
8
ns
6
Delay time, ECLKIN low to ECLKOUT1 low
0.8
8
ns
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