參數(shù)資料
型號: TMX320C6414TGLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 70/140頁
文件大?。?/td> 2033K
代理商: TMX320C6414TGLZ
SPRS226H NOVEMBER 2003 REVISED AUGUST 2005
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
power-down mode logic
Figure 9 shows the power-down mode logic on the C6414T/C6415T/C6416T.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN
RESET
CLKOUT6
PD3
Internal
Peripherals
CLKOUT4
Clock
Distribution
and Dividers
External input clocks, with the exception of CLKIN, are
not
gated by the power-down mode logic.
TMS320C6414T/15T/16T
Figure 9. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 1510)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 10 and described in Table 32.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU
and Instruction Set Reference Guide
(literature number SPRU189).
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