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參數(shù)資料
| 型號： | TMX320C6205GHK200 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 54/72頁 |
| 文件大?。?/td> | 1143K |
| 代理商： | TMX320C6205GHK200 |
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SPRS106G OCTOBER 1999 REVISED JULY 2006
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP
(see Figure 33)
NO.
200
UNIT
MIN
2P§
P1
MAX
2
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X ext
ns
3
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
9
ns
CLKR ext
2
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
6
ns
CLKR ext
3
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
8
ns
CLKR ext
0.5
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
4
ns
CLKR ext
3
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
9
ns
CLKX ext
2
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
CLKX ext
6
3
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
The minimum CLKR/X pulse duration is either (P1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P1) = 9 ns as the minimum CLKR/X pulse
duration.
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