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| 型號(hào)： | TMX320C6205GHK200 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 18/72頁(yè) |
| 文件大小： | 1143K |
| 代理商： | TMX320C6205GHK200 |
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SPRS106G OCTOBER 1999 REVISED JULY 2006
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions (Continued)
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
EMIF DATA (CONTINUED)
ED8
M17
ED7
N19
ED6
P19
ED5
N15
ED4
P18
I/O/Z
External data
ED3
P17
ED2
R19
ED1
R18
ED0
R17
EMIF ASYNCHRONOUS MEMORY CONTROL
ARE
U14
O/Z
Asynchronous memory read-enable
AOE
W14
O/Z
Asynchronous memory output-enable
AWE
V14
O/Z
Asynchronous memory write-enable
ARDY
W15
I
Asynchronous memory ready input
EMIF SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10
U19
O/Z
SDRAM address 10 (separate for deactivate command)
SDCAS/SSADS
V19
O/Z
SDRAM column-address strobe/SBSRAM address strobe
SDRAS/SSOE
U18
O/Z
SDRAM row-address strobe/SBSRAM output-enable
SDWE/SSWE
T17
O/Z
SDRAM write-enable/SBSRAM write-enable
EMIF BUS ARBITRATION
HOLD
P14
I
Hold request from the host
HOLDA
V15
O
Hold-request-acknowledge to the host
TIMER 0
TOUT0
E5
O
Timer 0 or general-purpose output
TINP0
C5
I
Timer 0 or general-purpose input
Timer 1
TOUT1
A5
O
Timer 1 or general-purpose output
TINP1
B5
I
Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3
A17
DMAC2
B17
O
DMA action complete
DMAC1
C16
DMAC0
A18
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
A12
I
External clock source (as opposed to internal)
CLKR0
B9
I/O/Z
Receive clock
CLKX0
C9
I/O/Z
Transmit clock
DR0
A10
I
Receive data
DX0
B10
O/Z
Transmit data
FSR0
E10
I/O/Z
Receive frame sync
FSX0
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
A9
I/O/Z
Transmit frame sync
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