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參數(shù)資料
| 型號： | TMUX03155 |
| 廠商： | Lineage Power |
| 英文描述： | STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer(STS-3/STM-1 (AU-4)多路復(fù)用器/多路分解器) |
| 中文描述： | STS-3/STM-1（非盟- 4）多路復(fù)用器/多路解復(fù)用器（STS-3/STM-1（非盟- 4）多路復(fù)用器/多路分解器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 261K |
| 代理商： | TMUX03155 |
Product Brief
February 1998
TMUX03155 STS-3/STM-1 (AU-4) Multiplexer/Demultiplexer
7
Lucent Technologies Inc.
STS-3/STM-1 (AU-4) Scramble Enable
Scrambling of the STS-3/STM-1 (AU-4) signal is provi-
sionable. A frame synchronous scrambling sequence
1 + x
6
+ x
7
is used.
STS-3/STM-1 (AU-4) B1, B2, and B3 BIP
Generation
The device will generate a B1-BIP-8, B2-BIP-24, and a
B3-BIP-8 (AU-4 mode only) on the output signal. Each
BIP calculator can be programmed to insert an inverted
BIP value.
STS-3/STM-1 (AU-4) Loopback Control
The output STS-3/STM-1 (AU-4) signal can be
replaced by the receive STS-3/STM-1 (AU-4) signal
under software control.
STS-3/STM-1 (AU-4) Output Interface
The transmit STS-3/STM-1 (AU-4) output can be serial
at 155.52 Mbits/s, nibble at 38.88 Mbits/s, or byte paral-
lel at 19.44 Mbits/s. The data is clocked out of the
device on the rising edge of the clock. This clock can
be inverted before leaving the device. When provi-
sioned in the parallel or nibble mode, an even or odd
parity bit is generated per transfer.
The output clock, sync, and data signals can be placed
in a high-impedance state under user control. Unused
outputs in serial and nibble mode will be placed in a
high-impedance state automatically by the device.
Receive Direction Overview
The following functions are performed in the receive
direction: Input Retime, STS-3/STM-1 (AU-4) Framing,
Loss of Signal, Loopback Select Logic, STS-3/STM-1
(AU-4) Frame Synchronous Descrambling, TOAC
Drop, B1, B2, and B3 Checking, Monitoring Functions,
Pointer Interpretation, Data Demultiplex and Conver-
sion, STS-1/AU-3 Output Byte Control, B1 and B2 Gen-
erate, STS-1/AU-3 Output Scramble, and Output
Selection Logic.
Input Retime
The device accepts either a serial 155.52 MHz-Mbits/s,
nibble 38.88 MHz-Mbits/s, or byte parallel
19.44 MHz-Mbits/s clock-data STS-3/STM-1 (AU-4)
input. The user can select on which edge of the clock to
retime the data. If in nibble or parallel mode, an odd/
even parity bit is verified per transfer; otherwise, this
indicator is disabled.
STS-3/STM-1 (AU-4) Framing
The device will frame on the input STS-3/STM-1 (AU-4)
signal. The state of the framer as well as any changes
to this state will be reported.
Framing Algorithm
The 32-bit (A1-2, A1-3, A2-1, A2-2) framing pattern will
be used in the frame detection. The device will be con-
sidered out of frame until
two
successive framing pat-
terns separated in time by 125
μ
s occur without
framing byte errors.
The device will be considered in frame until
five (SDH)/
four (SONET)
successive frames separated in time by
125
μ
s occur with errored framing patterns. If the
framer transitions to the out-of-frame state, the framer
will remain synchronized to the last known frame
boundary or the latest detected unerrored framing pat-
tern.
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