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| 型號： | TMS6641648A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動態(tài)隨機存取記憶體 |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 958K |
| 代理商： | TMS6641648A |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
20
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating ambient
temperature (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
- 8 (x8/x4)
MIN
- 8 (x16)
MIN
- 8A (x8/x4)
MIN
UNIT
MAX
MAX
MAX
VOH
High-level output
voltage
IOH = –2 mA
2.4
2.4
2.4
V
VOL
Low-level output
voltage
IOL = 2 mA
0.4
0.4
0.4
V
II
Input current
(leakage)
0 V
≤
VI
≤
VCC + 0.3 V,
All other pins = 0 V to VCC
0 V
≤
VO
≤
VCCQ
Output disabled
±
10
±
10
±
10
μ
A
IO
Output current
(leakage)
±
10
±
10
±
10
μ
A
ICC1
Operating
current
Burst length = 1,
tRC
tRC
IOH/IOL = 0 mA
(see Notes 3, 4, and 5)
CKE
VIL MAX, tCK = 15 ns
(see Note 6)
CAS latency = 2
115
125
95
mA
CAS latency = 3
125
135
125
mA
ICC2P
Precharge
standby current
in power-down
mode
1
1
1
mA
ICC2PS
CKE and CLK
(see Note 7)
VIL MAX, tCK =
∞
1
1
1
mA
ICC2N
Precharge
standby current
in
non-power-down
mode
CKE
(see Note 6)
VIH MIN, tCK = 15 ns
40
40
40
mA
ICC2NS
tCK =
(see Note 7)
5
5
5
mA
ICC3P
Active standby
current in
power-down
mode
CKE
(see Notes 3 and 6)
VIL MAX, tCK = 15 ns
8
8
8
mA
ICC3PS
CKE and CLK
(see Notes 3 and 7)
VIL MAX, tCK =
∞
8
8
8
mA
ICC3N
Active standby
current in
non-power-down
mode
CKE
(see Notes 3 and 6)
VIH MIN, tCK = 15 ns
50
55
50
mA
ICC3NS
CKE
(see Notes 3 and 7)
VIH MIN, CLK
VIL MAX, tCK =
∞
15
15
15
mA
ICC4
Burst current
Page burst, IOH/IOL = 0 mA
All banks activated,
(see Notes 8, 9, and 10)
CAS latency = 2
165
165
120
mA
CAS latency = 3
225
245
165
mA
ICC5
Auto-refresh
current
tRC
(see Notes 4 and 7)
tRC MIN
CAS latency = 2
150
150
150
mA
CAS latency = 3
150
150
150
mA
ICC6
Self-refresh
current
CKE
VIL MAX
1
1
1
mA
NOTES:
2. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
3. Only one bank is activated.
4. tRC
tRC MIN
5. Control, DQ, and address inputs change state twice during tRC.
6. Control, DQ, and address inputs change state once every 30 ns.
7. Control, DQ, and address inputs do not change state (stable).
8. 4-bank ping-pong, burst length = 4, nCCD = 4 cycles, data pattern 0011.
9. Column address and bank address increment every 4 cycles.
10. A tCK of 10 ns is used to obtain ICC4 for CL3 of the -8A speed grade.
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