參數(shù)資料
型號: TMS32C6411GLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 84/119頁
文件大?。?/td> 1742K
代理商: TMS32C6411GLZ
SPRS196H MARCH 2002 REVISED JULY 2004
84
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUTx
CEx
BE[3:0]
EA[12:3]
ED[31:0]
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
AWE/SDWE/SWE
EA13
EA[22:14]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
PDT
14
14
PDTR/W
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
Figure 28. SDRAM Write Command
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