參數(shù)資料
型號： TMS32C6411GLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 38/119頁
文件大?。?/td> 1742K
代理商： TMS32C6411GLZ
SPRS196H MARCH 2002 REVISED JULY 2004
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
DEVICE CONFIGURATION
LEND
E16
I/O/Z
IPU
Device Endian mode
LEND:
0
1
–
Big Endian
Little Endian (default mode)
HD5/AD5§
Y1
I/O/Z
Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-k
resistor
pullup/pulldown resistor on the HD5 pin:
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
PCI_EN
AA4
I
IPD
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals. For more details, see the Device Configurations section of this data sheet.
EEAI
B17
I/O/Z
IPD
PCI EEPROM Auto-Initialization (EEAI) via external EEPROM
If
the PCI peripheral is disabled (PCI_EN pin = 0), this pin must
not
be pulled up.
EEAI: 0
PCI auto-initialization through EEPROM is disabled (default).
1
PCI auto-initialization through EEPROM is enabled.
BOOTMODE1
D18
I/O/Z
IPU
Boot mode. Default is reserved. External pullup and/or pulldown resistors must be used to
select a valid bootmode configuration.
BOOTMODE[1:0]:
00 –
01
10
11
No boot
HPI boot
Reserved
EMIF 8-bit ROM boot with default timings (default mode)
BOOTMODE0
C18
IPD
ECLKIN_SEL1
B18
I/O/Z
IPD
EMIF clock mode select
ECLKIN_SEL[1:0]: 00 –
ECLKIN (default mode)
CPU/4 Clock Rate
CPU/6 Clock Rate
Reserved
ECLKIN_SEL0
A18
01
10
11
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AC7
I
Device reset
NMI
B4
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
GP7/EXT_INT7
AF4
General-purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
). The
default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently
selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
General-purpose input/output (GPIO) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at default.
GPIO 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GPIO 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GPIO 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GPIO 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GPIO 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GPIO 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
GPIO 3 pin (
I/O/Z
).
GP6/EXT_INT6
AD5
I/O/Z
IPU
GP5/EXT_INT5
AE5
GP4/EXT_INT4
GP15/PRST§
GP14/PCLK§
GP13/PINTA§
GP12/PGNT§
GP11/PREQ§
GP10/PCBE3§
GP9/PIDSEL§
AF5
G3
F2
G4
J3
I/O/Z
F1
L2
M3
GP3
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used, unless otherwise noted.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
AC6
IPD
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