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參數(shù)資料
| 型號： | TMS320UVC5409 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processor(定點(diǎn)DSP) |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器（定點(diǎn)DSP）的 |
| 文件頁數(shù)： | 5/35頁 |
| 文件大?。?/td> | 443K |
| 代理商： | TMS320UVC5409 |
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TMS320UVC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS102 – APRIL 1999
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
terminal functions
The following table lists each signal, function, and operating mode(s) grouped by function.
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(MSB)
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen
address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O while the upper seven
address pins (A16 to A22) are only used to address external program space. These pins are placed in the
high-impedance state when the hold mode is enabled, or when OFF is low.
(LSB)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(MSB)
(LSB)
I
These pins can be used to address internal memory via the HPI when the HPI16 pin
is high (A0 – A15).
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
I/O/Z
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
I/O
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are
multiplexed to transfer data between the core CPU and external data/program
memory or I/O devices. The data bus is placed in the high-impedance state when not
outputting or when RS or HOLD is asserted. The data bus also goes into the
high-impedance state when OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by
floating, unused pins. These bus holders also eliminate the need for external bias
resistors on unused pins. When the data bus is not being driven by the ’UVC5409, the
bus holders keep the pins at the previous logic level. The data bus holders on the
’UVC5409 are disabled at reset and can be enabled/disabled via the BH bit of the
bank-switching control register (BSCR).
(LSB)
(LSB)
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
I
External user interrupts. INT0 –INT3 are prioritized and are maskable by the interrupt mask register and the interrupt
mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register.
NMI
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
I = Input, O = Output, Z = High-impedance, S = Supply
A
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